• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.9-11
• /
• 2001

차세대 고속 DRAM기술에 사용될 금속인 Cu의 확산 방지막(diffusion harrier) 물질로는 Ta 또는 W 같은 Refractory metal 이 융점(melting point)이 높고 저항값이 낮아 많이 연구 보고되고 있으나, 본 논문에서는 초고주파 소자에서 Au의 확산 방지 막으로 많이 사용되고 있으며. 선택적 증착이 용이한 Pt과 Ni를 MOS 소자의 Cu 확산 방지 막으로 적용하며 어닐링한 후 소자의 게이트 산화막 누설전류($I_{leak}$), 그리고. Si/$SiO_2$ 계면의 trap density 등의 변이를 측정하여 Cu가 소자의 특성 열화에 미치는 영향을 연구하였다. 실험 결과 Pt/Ti($200{\AA}/100{\AA}$)를 적용한 경우 소자 측성 열화가 가장 적었으며. 이는 Copper의 확산 방지막으로 Pt/Ti를 사용하여 전기적 특성 및 계면 특성을 개선시킬 수 있음을 보여 주었다. 이는 SIMS Profile을 통해서도 확인하였다.

• E2M - 전기 전자와 첨단 소재
• /
• 제16권9호
• /
• pp.62.1-62
• /
• 2003

Silicon oxide with thickness lee than 9 nm is fabricated by tube furnace oxidation. Nitrogen is added to dilute the oxidation rate. Aluminum dots with radius of 0.05 cm are deposited on the oixde. High frequency capacitance-voltage(HF C-V), conductance-voltage(G-V) and current-voltage(I-V) characteristics are measured. Annealing under nitrogen atmosphere is carried out with different time and at different temperature. Densities of the interface states before and after annealing are compared. After annealing, a decrease in density of the interface states is found. Experiments show that 45$0^{\circ}C$ annealing for 30 minutes has the lowest density of the interface states.

• 전자공학회논문지D
• /
• 제35D권8호
• /
• pp.38-43
• /
• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• 산업공학
• /
• 제12권4호
• /
• pp.496-505
• /
• 1999

Quality of Service(QoS) is the collective effect of service performances and has a direct impact on customer satisfaction. Although QoS is subjective, network performance parameters contributing to QoS can be measured physically. Therefore overall customer satisfaction for each test condition of the performance parameters is evaluated by asking respondents to indicate his or her opinion on a five-category rating scale i.e., excellent, good, fair, poor, and unsatisfactory. The opinion data resulting from the test can then be used to measure and analyze QoS from the customers' viewpoints. In this papaer, we consider two methods for analyzing the opinion data: MOS method and Cumulative Probability Curve method. The former evaluates an arithmetic mean of the opinion scores which quantify the surveyed opinions of respondents. The latter uses graphical and analytical models which are based on the distribution of the opinions rather than an arithmetic mean. The advantages, disadvantages, and an alternative of each method are discussed, together with future directions of research.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.559-560
• /
• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• Journal of Nutrition and Health
• /
• 제22권6호
• /
• pp.497-506
• /
• 1989

To investigate the effect of levels of dietary protein and age on bone metabolism 40% and 5% casein were fed to the rats of 2 & 13 months of age for 12 weeks. High protein groups showed higher bone weight and Ca content than low protein groups and urinary Ca loss was increased in high protein groups but the difference disappeared gradually. A significant increase in urinary hydroxyproline excretion was noted in high protein groups of both age. Another short term study was undertaken to study if the above effect was related with renal function or PTH. Extremely high and low protein diets(60%, 6%) were fed to the rats of different ages(6wks, 6mos.) for 2 weeks, Urinary Ca excretion was significantly increased in high protein groups of young and aged rats and GFR was increased as well. There was no difference in serum iPTH levels between low and high protein groups, but it was elevated in aged rats. Alkaline phosphatase activity was higher in young rats, reflecting faster bone formation. The observed hypercalciuria in high protein groups, especially in aged rats, seems to be related to higher GFR, and PTH dose not appear to be a major mediator.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
• /
• pp.297-300
• /
• 2005

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated using sputter deposited amorphous silicon (a-Si) precursor films are investigated. The a-Si films were deposited on flexible polymer substrates using argon-helium mixture gases to minimize the argon incorporation into the film. The precursor films were then laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated pMOS TFT showed field-effect mobility of $32.4cm^2/V{\cdot}s$ and on/off ratio of $10^6$.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1996년도 추계학술대회 논문집
• /
• pp.113-116
• /
• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• 전자공학회논문지A
• /
• 제33A권4호
• /
• pp.112-120
• /
• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• 전자공학회논문지D
• /
• 제34D권6호
• /
• pp.43-49
• /
• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.