• 한국결정성장학회지
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• 제14권1호
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• pp.6-11
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• 2004

Bias 인가된 hot filament CVD 방법을 이용해 티타늄을 RF sputtering 법으로 고속도강에 피복하여 중간 층으로 한 후 다이아몬드 박막을 피복할 때 bias 전압의 영향과 계면 층의 특성을 조사하였다. 다이아몬드 증착 시 bias가 인가될 경우 필라멘트에서 전자 방출이 촉진되어 다이아몬드 핵생성과 성장을 촉진시켰으며 본 실험에서의 최적 증착 조건은 증착 압력 20 torr, bias 인가전압 200V, 기판온도 $700^{\circ}C$로 나타났다. 강에의 다이아몬드 박막 형성 시 중간 층으로서의 티타늄은 Fe 및 C에 대한 확산도가 높고 탄화물 형성 원소이므로 다이아몬드 핵생성 및 성장에 적합한 원소로 나타났다.

• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Transactions on Electrical and Electronic Materials
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• 제6권2호
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• pp.57-62
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• 2005

Using intense pulsed ion beam evaporation technique, we have succeeded in the preparation of poly crystalline silicon thin films without impurities on silicon substrate. Good crystallinity and high deposition rate have been achieved without heating the substrate by using lEE. The crystallinity of poly-Si film has been improved with the high density of the ablation plasma. The intense diffraction peaks of poly-Si thin films could be obtained by using the substrate bias system. The crystallinity and the deposition rate of poly-Si thin films were increased by applying (-) bias voltage for the substrate.

• Journal of Advanced Marine Engineering and Technology
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• 제18권2호
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• pp.54-63
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• 1994

Mg thin films were prepared on SPCC(cold-rolled steel) substrates by vasuum evapoaration and ion-plating. The influence of argon gas pressure and substrates bias voltage on the crystal orientation and morphology of the film was determined by using X-ray diffraction and scanning electron micrography (SEM), respectively. And the effect of crystal orientation and morphology of the Mg thin films on corrosion behavior was estimated by measuring the anodic polarization curves in deaerated 3% NaCl solution. The crystal orientation of the Mg films deposited at high argon gas pressure exhibited a (002) preferred orientation, regardless of the substrate bias voltage. Film morphology changed from a columnar to a granular structure with the increase of argon gas pressure. The morphology of the films depended not only on argon gas pressure but also bias voltage ; i.e., the effect of increasing bias voltage was similar to that of decreasing argon gas pressure. The influences of argon gas pressure and bias voltage were explained by applying the adsorption inhibitor theory and the sputter theory. And also, this showed that the corrosion resistance of the Mg thin films can be changed by controlling the crystal orientaton and morphology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• 한국정보전자통신기술학회논문지
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• 제16권4호
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• pp.180-186
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• 2023

본 논문은 4세대 VNAND 공정으로 만들어진 고전압 SiO2 절연층 nMOSFET의 n⁺ 및 p⁺ poly-Si 게이트에서의 positive bias temperature instability(PBTI) 열화에 대해 비교하고 각각의 메커니즘에 대해 분석한다. 게이트 전극 물질의 차이로 인한 절연층의 전계 차이 때문에 n⁺/nMOSFET의 열화가 p⁺/nMOSFET의 열화보다 더 클 것이라는 예상과 다르게 오히려 p⁺/nMOSFET의 열화가 더 크게 측정되었다. 원인을 분석하기 위해 각각의 경우에 대해 interface state와 oxide charge를 각각 추출하였고, 캐리어 분리 기법으로 전하의 주입과 포획 메커니즘을 분석하였다. 그 결과, p⁺ poly-Si 게이트에 의한 정공 주입 및 포획이 p⁺/nMOSFET의 열화를 가속시킴을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• 한국재료학회지
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• 제13권7호
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• pp.415-419
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• 2003

Carbon nanotubes were formed on silicon substrate using microwave plasma-enhanced chemical vapor deposition method. The possibility of carbon nanotubes formation was related to the thickness of nickel catalyst. The growth behavior of carbon nanotubes under the identical thickness of nickel catalyst was strongly dependent on the magnitude of the applied bias voltage. High negative bias voltage (-400 V) gave the vertically well-aligned carbon nanotubes. The vertically well-aligned carbon nanotubes have the multi-walled structure with nickel catalyst at the end position of the nanotubes.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• 전자공학회논문지D
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• 제35D권12호
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• pp.41-47
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• 1998

효율적인 바디 바이어스와 자유로운 공급 전압(supply voltage)으로 동작할 수 있는 동적 문턱 전압(dynamic threshold voltage)제어를 이용한 고속, 저전력 SOI 인버터를 새로이 제안하였다. 제안된 회로의 특성을 BSIM3SOI 회로 시뮬레이터와 ATLAS 소자 시뮬레이터를 이용해 검증하였고 다른 SOI 회로와 비교함으로써 제안한 회로가 우수한 성능을 가짐을 보였다. 제안된 회로는 1.5V의 공급 전압에서 같은 전력 소모를 갖는 기존의 SOI 회로보다 27% 빠르게 동작하였다.