• 제목/요약/키워드: High-k gate dielectrics

검색결과 70건 처리시간 0.026초

Optimization of Gate Stack MOSFETs with Quantization Effects

  • Mangla, Tina;Sehgal, Amit;Saxena, Manoj;Haldar, Subhasis;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권3호
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    • pp.228-239
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    • 2004
  • In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

Reliability of Multiple Oxides Integrated with thin $HfSiO_x$ gate Dielectric on Thick $SiO_2$ Layers

  • Lee, Tae-Ho;Lee, B.H.;Kang, C.Y.;Choi, R.;Lee, Jack-C.
    • 마이크로전자및패키징학회지
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    • 제15권4호
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    • pp.25-29
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    • 2008
  • Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

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Low-operating voltage Pentacene FETs with High dielectric constant polymeric gate dielectrics and its hyteresis behavior

  • Park, Chan-Eon
    • 한국고분자학회:학술대회논문집
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    • 한국고분자학회 2006년도 IUPAC International Symposium on Advanced Polymers for Emerging Technologies
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    • pp.168-168
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    • 2006
  • Low-operating voltage organic field-effect transistors (OFETs) have been realized with high dielectric constant (${\kappa}$) polymer such as cyanoethylated poly vinyl alcohol (CR-V, ${\kappa}=12$). Since the $high-{\kappa}$polymers are likely to contain water and ionic impurities, large hysteresis and considerable leakage current are frequently observed in OFETs. To solve these problems, we cross-linked the CR-V by using a cross-linking agent. Cross-linked CR-V dielectrics showed high dielectric constant of 11.1 and good insulating properties, resulting in a high capacitance ($81nF/cm^{2}$ at 1MHz) at 120 nm of dielectric thickness. Pentacene FETs with cross-linked CR-V dielectrics exhibited high carrier mobility ($0.72\;cm^{2}/Vs$), small subthreshold swing (185 mV/dec) and little hysteresis at low-operating voltage (${\Leq}-3V$).

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Simple Route to High-performance and Solution-processed ZnO Thin Film Transistors Using Alkali Metal Doping

  • 김연상;박시윤;김경준;임건희
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.187-187
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    • 2012
  • Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

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엔지니어드된 터널 절연막과 전하트랩층에 고유전 물질을 적용한 전하 트랩형 메모리 캐패시터의 메모리 특성 개선 (Improvement in Memory Characteristics of Charge Trap Memory Capacitor with High-k Materials as Engineered Tunnel Dielectrics and Charge Trap Layer)

  • 김민수;유희욱;박군호;오세만;정종완;이영희;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.408-409
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    • 2009
  • The memory characteristics of charge trap memory capacitor with high-k materials were investigated. I-V characteristics of the fabricated device with band gap engineered tunneling gate stacks consisted of $SiO_2$, $ZrO_2$, $Al_2O_3$ dielectrics were evaluated and compared with the one consisted of $SiO_2$ tunneling dielectric. The memory capacitor including engineered tunneling dielectrics of ($Al_2O_3/ZrO_2/SiO_2$) shows the fastest PIE speed and long data retention time.

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Polymer Dielectrics and Orthogonal Solvent Effects for High-Performance Inkjet-Printed Top-Gated P-Channel Polymer Field-Effect Transistors

  • Baeg, Kang-Jun;Khim, Dong-Yoon;Jung, Soon-Won;Koo, Jae-Bon;You, In-Kyu;Nah, Yoon-Chae;Kim, Dong-Yu;Noh, Yong-Young
    • ETRI Journal
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    • 제33권6호
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    • pp.887-896
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    • 2011
  • We investigated the effects of a gate dielectric and its solvent on the characteristics of top-gated organic field-effect transistors (OFETs). Despite the rough top surface of the inkjet-printed active features, the charge transport in an OFET is still favorable, with no significant degradation in performance. Moreover, the characteristics of the OFETs showed a strong dependency on the gate dielectrics used and its orthogonal solvents. Poly(3-hexylthiophene) OFETs with a poly(methyl methacrylate) dielectric showed typical p-type OFET characteristics. The selection of gate dielectric and solvent is very important to achieve high-performance organic electronic circuits.

Characteristics of Si Nano-Crystal Memory

  • Kwangseok Han;Kim, Ilgweon;Hyungcheol Shin
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제1권1호
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    • pp.40-49
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    • 2001
  • We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}V_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

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$Ta/TaN_x$ Metal Gate Electrodes for Advanced CMOS Devices

  • Lee, S. J.;D. L. Kwong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권3호
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    • pp.180-184
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    • 2002
  • In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

MOS 소자의 대체 게이트 산화막으로써 $HfO_{2}/HfSi_{x}O_{y}$ 의 구조 및 전기적 특성 분석 (Structural and electrical characterizations of $HfO_{2}/HfSi_{x}O_{y}$ as alternative gate dielectrics in MOS devices)

  • 강혁수;노용한
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.45-49
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    • 2001
  • We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

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분광 타원계측기를 이용한 고굴절률 게이트 산화막의 광물성 분석 (Optical Properties of High-k Gate Oxides Obtained by Spectroscopic Ellipsometer)

  • 조용재;조현모;이윤우;남승훈
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 추계학술대회
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    • pp.1932-1938
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    • 2003
  • We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

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