JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimization of Gate Stack MOSFETs with Quantization Effects

  • Mangla, Tina (Semiconductor Device Research Laboratory, Department of Electronic Science University of Delhi South Campus) ;
  • Sehgal, Amit (Semiconductor Device Research Laboratory, Department of Electronic Science University of Delhi South Campus) ;
  • Saxena, Manoj (Department of Physics & Electronics, Deen Dayal Upadhayaya College, University of Delhi) ;
  • Haldar, Subhasis (Department of Physics, Motilal Nehru College, University of Delhi) ;
  • Gupta, Mridula (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus) ;
  • Gupta, R.S. (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus)
  • Published : 2004.09.30
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Abstract

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

Keywords

References

  1. M Ono, M Saito, T Yoshitomi, C Fiegna, T Ohguro and H Iwai, 'A 40 nm gate length nMOSFETs', IEEE Trans Electron Devices, Vol 42, p 1822-30,1995 https://doi.org/10.1109/16.464413
  2. Y Taur, D A Buchanan, W Chen, D J Frank, K E Ismail, S H Lo, G A Sai-Halasz, R G Viswanathan, H J C Warn, S J Wind, H S Wong, 'CMOS scaling into the nanometre regime', Proceeding IEEE, Vol 85, P 486-504, 1997 https://doi.org/10.1109/5.573737
  3. S H Lo, D A Buchanan, Y Taur, W Wang, 'Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs', IEEE Trans Electron Device Letter, Vol 18, p 209-11, 1997 https://doi.org/10.1109/55.568766
  4. E M Vogel, K Z Ahmed, B Hornug, W K Henson, P K McLarty, G Lucovsky, J R Hauser, J J Wortman, 'Modeled tunnel currents for high dielectric constant dielectrics', IEEE Trans Electron Devices, Vol 45. p 1350-4,1998 https://doi.org/10.1109/16.678572
  5. Q Lu, D Park, A Kalnitsky, C Chang, C C Cheng, S P Tay, T J King and C Hu, 'Leakage current comparison between ultra-thin $Ta_2O_5$ films and conventional gate dielectrics'. IEEE Trans Electron Devices Letter, Vol 19, p 341-2, 1998 https://doi.org/10.1109/55.709635
  6. D Park, Y King, Q Lu, T J King, C Hu, A Kalnitsky, S P Tay, C C Cheng, 'Transistor characteristics with $Ta_2O_5$ gate dielectric', IEEE Trans Electron Devices Letter, Vol 19, p 441-3, 1998 https://doi.org/10.1109/55.728906
  7. X Guo, X Wang, Z Juo, T P Ma, T Tamagawa, 'High-quality ultrathin (1.5nm) $TiO_2/Si_3N_4$ gate dielectric for deep sub-micron CMOS technology', IEDM Technical Digest, p 137-140, 1999 https://doi.org/10.1109/IEDM.1999.823864
  8. W J Qi, R Nieh, B H Lee, L Kang, Y Jeon, K Onishi, T Ngai, S Banerjee, J C Lee, 'MOSCAP and MOSFET characteristics using $ZrO_2$ gate dielectric deposited directly on Si', IEDM Technical Digest, p 145-81, 1999 https://doi.org/10.1109/IEDM.1999.823866
  9. B H Lee, L Kang, W J Qi, R Nieh, Y Jean. K Onishi, J C Lee, 'Ultrathin hafnium oxide with low leakage and excellent reliability for gate dielectric application', IEDM Technicai Digest, p 133-6, 1999 https://doi.org/10.1109/IEDM.1999.823863
  10. G D Wilk, R M Wallace, J M Anthony, 'Hafnium and zirconium silicates for advanced gate dielectrics', J Appl Phys, Vol 87, p 484-92, 2000 https://doi.org/10.1063/1.371888
  11. B Cheung, Min Cao, R Rao, A lnani, P V Voorde, W M Greene, J M C Stork, Z Yu, P M Zeitzoff, J C S Woo, 'The Impact of $High-{\lambda}$ gate dielectrics and metal gate electrode on sub-100nm MOSFETs', IEEE Trans Electron devices, Vol 46, p 1537-42, 1999 https://doi.org/10.1109/16.772508
  12. F. Stern and W. E. Howard, 'Properties of semiconductor surface inversion layer in the electric quantum limit', Phys Rev., Vol. 163. p. 816-35, 1967 https://doi.org/10.1103/PhysRev.163.816
  13. T. Ando, A. B. Fowler, F. Stern, 'Electronic properties of two-dimensional systems', Rev. Mod. Phys., Vol. 54, p.437-672, 1982 https://doi.org/10.1103/RevModPhys.54.437
  14. M. J. Van Dort, P. H. Woerlee, A. J. Walker, C. A. H. Juffermans and H. Lifka, 'Influence of high substrate doping levels on the threshold voltage and the mobility of deep-sub micrometer MOSFETs', IEEE Trans. Electron Devices Vol. 39, p. 932-8, 1992 https://doi.org/10.1109/16.127485
  15. A. Hartstein and . N. F. Albert, 'Determination of the inversion-layer thickness from capacitance measurement of metal-oxide-semiconductor field-effect transistor with ultra thin oxide layers', Phys. Rev. B, Vol. 38. p. 1235-40, 1988 https://doi.org/10.1103/PhysRevB.38.1235
  16. Y. Ohkura, 'Quantum effect in Si n-MOS inversion layer at high substrate concentration', Solid-State Electron, Vol. 33, p. 1581-5, 1990 https://doi.org/10.1016/0038-1101(90)90138-5
  17. T. Janik and B. Majkusiak, 'Influence of carrier energy quantization on threshold voltage of metal-oxide-semiconductor transistor', J. Appl. Phys., Vol. 75, p. 5186-90, 1994 https://doi.org/10.1063/1.355766
  18. R. Versari and B. Ricco, 'Scaling of maximum capacitance of MOSFET with ultra-thin oxide', Electronic letters, Vol. 34, p. 2175-6, 1998 https://doi.org/10.1049/el:19981471
  19. G. Baccarani and M. R. Worderman, 'Tansconductance degradation in thin-oxide MOSFETs', IEEE Trans. Electron Devices, Vol. 30, p. 1295-1304, 1983 https://doi.org/10.1109/T-ED.1983.21290
  20. K. Ip. Brian and R. Brews Johnn, 'Quantum effects upon drain current in a biased MOSFET', IEEE Trans. Electron Devices, Vol. 45, p. 2213-21, 1998 https://doi.org/10.1109/16.725256
  21. M. J. Van Dort, P. H. Woerlee, A. J. Walker, 'A simple model for quantisation effects in heavily-doped silicon MOSFET at inversion conditions', Solid-State Electron, Vol. 37, p. 411-4, 1994 https://doi.org/10.1016/0038-1101(94)90005-1
  22. T. Janik and B. Majkusiak, 'Analysis of the MOS transistor based on the self-consistent solution to the Schrodinger and Poisson equations and on the local mobility model', IEEE Trans. Electron Devices, Vol. 45, p.1263-71, 1998 https://doi.org/10.1109/16.678531
  23. G. Chindalore, S. A. Hareland, S. Jallepalli, A. F. Tasch, C. M. Maziar, V. K. F. Chia and S. Smith, 'Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers', IEEE Trans. Electron Devices Letter, Vol. 18, p. 206-8, 1997 https://doi.org/10.1109/55.568765
  24. S. Jallepalli, J. Bude, W. K. Shih, M. R. Pinto, C. M. Maziar, A. F. Tasch, 'Electron and hole quantization and their impact on deep submicron silicon p-and n-MOSFET characteristics', IEEE Trans. Electron Devices, Vol. 44, p.297-302, 1997 https://doi.org/10.1109/16.557719
  25. C. Moglestue, 'Self-consistent calculation of electron and hole inversion charges at silicon-silicon dioxide interfaces', J. Appl. Phys., Vol. 59 p. 3175-83,1986 https://doi.org/10.1063/1.336898
  26. F. Stern, 'Self-consistent results for n-Type Si inversion layers', Phys Rev B., Vol. 5, p. 4891-9, 1972 https://doi.org/10.1103/PhysRevB.5.4891
  27. N. Arora, MOSFET models for VLSI circuit simulation, Theory and practice, New York: Springer-Verlag, 1993
  28. C. H. Choi, P. R. Chidambaram, R. Khamankar, C.F. Machala, Z. Yu and R. W. Dutton, 'Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS', IEEE Trans. Electron Devices, Vol. 49, p. 1227-31, 2002 https://doi.org/10.1109/TED.2002.1013280
  29. S. A. Campbell, D. C. Gilmer, X. C. Wang, M. T. Hsieh, H. S. Kim, W. L. Gladfelter and J. Yan, 'MOSFETs transistors fabricated with high permittivity $TIO_2$ dielectrics', IEEE Trans. Electron Devices, Vol. 44, p. 104-9, 1997 https://doi.org/10.1109/16.554800
  30. Y. Ma, L. Liu, Z. Yu and Z. Li, 'On the degeneracy of quantized inversion layer in MOS structures', Solid-Slate Electron, Vol 44, p. 1925-9, 2000 https://doi.org/10.1016/S0038-1101(00)00171-4