• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1303-1308
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• 2004

This paper proposes a reduction method for the mis-operation analysis of the DC High Speed Circuit Breaker(HSCB) in electric railway substation system. The analysis method is based on present condition of operation which is a method for accuracy level up. There is reason to operation of HSCB that it is mis-operation of fault detection relay(50F), operation of ground fault relay(64P), and trouble of electric car. A countermeasure is relay resetting through field test, induction of GTOCB(Gate Turn Off Thyristor Circuit Breaker), HSVCB(High Speed Vacuum Circuit Breaker), coordination with electric car. The results presented in the paper can be used as a reference for maintenance free in electric railway substation system.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.396-402
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• 2006

Even the case DC circuit Breaker have good quality for interruption of high current like heavy load current, short-circuit current, the verification for small current breaking capability of circuit breaker should be performed. It comes from the reason DC small current breaking failure can be lead to break out second heavy fault condition and in the long run substation shutdown. In this paper, we can find the characteristics of DC small current and international test standard discription about small current breaking and one of the proper solution to get over it.

• Journal of IKEEE
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• v.22 no.3
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• pp.882-885
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• 2018

Recently, signal integrity on PCB (printed circuit board) becomes very important as the system operation speed increases. So far, PCB is customarily designed to minimize area and cost. However, ultra-high-speed PCB often fail to operate properly, unless it is precisely and carefully designed considering dielectric characteristics, line width, line spacing, and impedance matching. This paper surveys many problems in ultra-high-speed PCB and various design methods to mitigate them.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.513-513
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• 2000

An integrable circuit technique for implementing high-speed analog two-input Max/Min circuit is described. The realization method is suitable for fabrication using CMOS technology. The proposed circuit comprises a current mirror and electronic switch connected with a absolute value circuit. The maximum or minimum operation of the proposed circuit can be selected by an external control voltage. The proposed analog Max/Min circuit has a very sharp transfer characteristic and is suitable for real-time systems. Simulation results verified the circuit performances are agreed with the expected values.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.975-978
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• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.188-194
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• 2000

This study is about fault detection and fault area detection of LV circuit in Cab Cubicle system which have control of train to keep safety in High Speed Train. LV circuit is operated with diagnosis system like safety system. In this paper, we suggest a design and an implementation method to detect fault or to detect fault area automatically about LV circuit. The implemented system is tested successfully after implementation of some function. We expect reduction to diagnosis area or repair time by fault area module