• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.1
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• pp.6-10
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• 2018

Ni germanide (NiGe) is a promising alloy material with small contact resistance at the source/drain (S/D) of Ge MOSFETs. However, it is necessary to reduce the specific contact resistance between NiGe and the doped Ge S/D region in high-performance MOSFETs. In this study, a novel method is proposed to reduce the specific contact resistance between NiGe and p-type Ge (p-Ge) using a Tb interlayer. The specific contact resistance between NiGe and p-Ge was successfully decreased with the introduction of the Tb interlayer. To investigate the mechanism behind the reduction in the specific contact resistance, the elemental distribution and crystalline structure of NiGe were analyzed using secondary ion mass spectroscopy and X-ray diffraction. It is likely that the reduction in specific contact resistance was caused by an increase in the concentration of boron in the space between NiGe and p-Ge due to the influence of the Tb interlayer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.1-6
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• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.5-6
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• 2005

High performance SiGe heterostructure metal-oxide-semiconductor field effect transistors(MOSFETs) were fabricated using well-controlled delta-doping of boron and SiGe/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe MOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^1$. However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}\sim10^{-2}$ in comparion with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• Journal of the Korean Vacuum Society
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• v.19 no.1
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• pp.14-21
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• 2010

Ge is one of the attractive channel materials for the next generation high speed metal oxide semiconductor field effect transistors (MOSFETs) due to its higher carrier mobility than Si. But the absence of a chemically stable thermal oxide has been the main obstacle hindering the use of Ge channels in MOS devices. Especially, the fabrication of gate oxide on Ge with high quality interface is essential requirement. In this study, $HfO_xN_y$ thin films were prepared by plasma-enhanced atomic layer deposition on Ge substrate. The nitrogen was incorporated in situ during PE-ALD by using the mixture of nitrogen and oxygen plasma as a reactant. The effects of nitrogen to oxygen gas ratio were studied focusing on the improvements on the electrical and interface properties. When the nitrogen to oxygen gas flow ratio was 1, we obtained good quality with 10% EOT reduction. Additional analysis techniques including X-ray photoemission spectroscopy and high resolution transmission electron microscopy were used for chemical and microstructural analysis.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.