• Proceedings of the KSME Conference
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• 2001.06a
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• pp.644-651
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• 2001

The purpose of this study is to develop the improvement method of MOV(Motor Operated Valve) operability without major modification or change of MOV which needs a great expense and manpower. We studied valve stem lubrication, stem packing thrust and actuator control switch which could give an major effect to MOV operability, and found the some consequences. First, the stem/stem-nut friction coefficient and stem factor is significantly effected by stem lubrication state. Second, the measured packing thrust value is appeared higer than the design value for tested valves and the preparation of optimal value selection criteria is needed. Finally, optimization of MOV control switch is another major factor for MOV operability and structual integrity.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.313-316
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• 2002

A SRM inverter has very low switching frequency. This results in reducing the burden for a high-speed of the gate-amp interface circuit. and the linearity of optocoupler is used to protect the intanteneous peak current for the stable operation In this paper, series resistor is used to equal the current sharing of each switching device and a linear gate-amp is proposed to protect the intanteneous peak current which occurs in transient state.

• Journal of Information Display
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• v.10 no.2
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• pp.54-61
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• 2009

The results of the optimization of the organic passivation process for fabricating thin-film transistors (TFTs) with a high aperture ratio on a seventh-generation glass (2200${\times}$1870 mm) substrate for LCD-TV panels are reported herein. The optimization of the organic passivation process has been verified by checking various factors, including the material properties (e.g., thickness, stain, etching, thermal reflow) and the effects on the TFT operation (e.g., gate/data line delay and display-driving properties). The two main factors influencing the organic passivation process are the optimization of the final thickness of the organic passivation layer, and the gate electrode. In conclusion, the minimum possible final thickness was found to be $2.42{\um}m$ via simulation and pilot testing, using the full-factorial design. The optimization of the organic passivation layer was accomplished by improving its brightness by over 10 cd/$m^2$ (ca. 2% luminance) compared to that of the conventional organic passivation process. The results of this research also help reduce the reddish stain on display panels.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitiations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

• Journal of Power Electronics
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• v.13 no.4
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• pp.729-736
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• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.31 no.9
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• pp.74-81
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• 1982

One of the stable thin film transistor fabricated by cadmium suifide with the anodized aluminium oxide as gate material. The principle of the operation for the device is based on the control mechanism of injected majority carricrs to the wide band gap semiconductor, that is cadmium sulfide, by means of the function of the gate control. The fabricated device constructed by evaporating CdS layer in the form of microcrystalline on the oxided thin film characterized by ea, 80 as voltage amplification factor, 1/100 mho as transconductance, 8 kohm as dynamic output resistance, furthermore gain band width products is about 15 MHz.

• Magazine of the Korean Society of Agricultural Engineers
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• v.37 no.2
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• pp.13.2-20
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• 1995

An water balance model was formulated to simulate the change in water levels at the estuary reservoir from sluice gate releases and the inflow hydrographs, and an one-di- mensional flood routing model was formulated to simulate temporal and spatial varia- tions of flood hydrographs along the estuarine river. Flow rates through sluice gates were calibrated with data from the estuary dam, and the results were used for a water balance model, which did a good job in predicting the water level fluctuations. The flood routing model which used the results from two hydrologic models and the water balance model simulated hydrographs that were in close agreement with the observed data. The flood forecasting model was found to be applicable to real-time forecasting of water level fluc- tuations with reasonable accuracies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.3
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• pp.292-297
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• 1987

High-speed GaAs IC Logic Gates being widely studied and developed in the develped countries were reanalysed and reexamined through SPICE simulations. And, furthermore, the detailed examinations of their characteristics such as operation characteristics and conditions, integration densities, service-ableness, and the limitation of both fabrication and application, give us a clue of the feasibility and application of them in the real integrated circuits. This paper will provide a reasonably good guide to set-up one of goals or future development of high-speed GaAs IC's being led by the goverment recently in our country.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.759-763
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• 2016

We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.