• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1355-1359
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• 2014

In the proposed work a 2D analytical modeling of single halo Triple material Surrounding Gate (SH-TMSG) MOSFET is developed. The Surface potential and Electric Field has been derived using parabolic approximation method and the simulation results are analyzed. The essential substantive is provided which elicits the deterioration of short channel effects and the results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.713-717
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• 2011

This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.223-229
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• 2017

This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of radiological science and technology
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• v.40 no.1
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• pp.13-18
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• 2017

The purpose of this study was to investigate CTDI (computed tomography dose index at center) for various phantom shapes, sizes, and compositions by using GATE (geant4 application for tomographic emission) simulations. GATE simulations were performed for various phantom shapes (cylinder, elliptical, and hexagonal prism PMMA phantoms) and phantom compositions (water, PMMA, polyethylene, polyoxymethylene) with various diameters (1-50 cm) at various kVp and mAs levels. The $CTDI_{100center}$ values of cylinder, elliptical, and hexagonal prism phantom at 120 kVp, 200 mAs resulted in 11.1, 13.4, and 12.2 mGy, respectively. The volume is the same, but $CTDI_{100center}$ values are different depending on the type of phantom. The water, PMMA, and polyoxymethylene phantom $CTDI_{100center}$ values were relatively low as the material density increased. However, in the case of Polyethylene, the $CTDI_{100center}$ value was higher than that of PMMA at diameters exceeding 15 cm ($CTDI_{100center}$ : 35.0 mGy). And a diameter greater than 30 cm ($CTDI_{100center}$ : 17.7 mGy) showed more $CTDI_{100center}$ than Water. We have used limited phantoms to evaluate CT doses. In this study, $CTDI_{100center}$ values were estimated and simulated by GATE simulation according to the material and shape of the phantom. CT dosimetry can be estimated more accurately by using various materials and phantom shapes close to human body.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.526-532
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• 2015

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS ($V_{GS}=13V$and $V_{DS}=13V$), the parallel shift of the transfer curve into a negative $V_{GS}$ direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (${\Delta}V_T$), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of ${\Delta}V_T$ were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy ($V{_O}^{2+}$). In addition, it was also confirmed that the wider channel width corresponds with more negative ${\Delta}V_T$. It means that both the donor-state creation and hole trapping can be enhanced due to the increase in self-heating as the width becomes wider. Lastly, all analyzed results were verified by reproducing transfer curves through TCAD simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.403-409
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• 2007

In this paper, effects of the trench angle($\theta$) on the breakdown voltage according to the process parameters of p-base region and doping concentrations of n-drift region in a Trench Gate IGBT (TIGBT) device were analyzed by computer simulation. Processes parameters used by variables are diffusion temperature, implant dose of p-base region and doping concentration of n-drift region, and aspects of breakdown voltage change with change of each parameter were examined. As diffusion temperature of the p-base region increases, depth of the p-base region increases and effect of the diffusion temperature on the breakdown voltage is very low in the case of small trench angle($45\;^{\circ}$) but that is increases 134.8 % in the case of high trench angle($90\;^{\circ}$). Moreover, as implant dose of the p-base region increases, doping concentration of the p-base region increases and effect of the implant dose on the breakdown voltage is very low in the case of small trench angle($45\;^{\circ}$) but that is increases 232.1 % in the case of high trench angle($90\;^{\circ}$). These phenomenons is why electric field concentrated in the trench is distributed to the p-base region as the diffusion temperature and implant dose of the p-base increase. However, effect of the doping concentration variation in the n-drift region on the breakdown voltage varies just 9.3 % as trench angle increases from $45\;^{\circ}$ to $90\;^{\circ}$. This is why magnitude of electric field concentrated in the trench changes, but direction of that doesn't change. In this paper, respective reasons were analyzed through the electric field concentration analysis by computer simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.3
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• pp.83-94
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• 2017

There is a two lane ECTS(Electronic Toll Collection System) that users can pass with 80kph high speed in SeoBusan Tall Gate. This system to be combined two hi-pass lanes for removing meddle-island have been operated successfully. But, the appearance of two Lane ETCS makes toll gate more complicated, so it is very important how to arrange effectively various tolling lanes. This study was trying to evaluate lane configuration for minimizing speed and speed deviation among all kinds of lanes including two Lane ETCS in seoul toll gate. That is, we selected all scenarios to be happened actually, and evaluated them using micro traffic simulation model (VISSIM). The results of this study showed that each alternative had a very different speed and speed deviation by lane each other, so we will be able to achieve effective operation and configuration of lanes in toll gate using scenario methodology.