• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• 전기전자학회논문지
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• 제24권4호
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• pp.1167-1171
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• 2020

본 연구에서는 상시불통형 p-GaN 전력반도체소자의 신뢰성 향상을 위해 p-GaN 게이트막 내부의 전계를 완화하고자 p-GaN 게이트 도핑농도의 계조화를 제안한다. TCAD 시뮬레이션으로 균일한 도핑농도를 갖는 소자와 문턱전압과 출력 전류 특성이 동일하도록 p형 농도를 계조화하고 최적화하였다. p-GaN 게이트층에서의 전계 감소로 소자의 게이트 신뢰성이 개선될 수 있을 것으로 판단된다.

• 한국ITS학회 논문지
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• 제14권3호
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• pp.50-62
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• 2015

최근 지하철 9호선은 2단계 연장구간의 개통으로 최대 240% 혼잡도를 기록하는 등 지옥철로 불리우며 역사 내 상습혼잡에 대한 문제점이 지속적으로 야기되고 있는 실정이다. 역사 내 혼잡은 이용객의 불쾌감 유발과 철도 운영 효율성을 저하시키는 요인이 되고 있다. 본 연구는 이러한 철도역사 내 상습혼잡 해소를 위해 철도 이용객 정보제공의 효과평가 방법론을 정립하고자 하였으며, 효과평가 방법론 중 승강장의 혼잡상황을 고려한 Gate Metering 사례 연구를 진행하였다. Gate Metering을 접목시킨 Micro Simulation 및 Pedestrian Simulation Tool을 선정하여 열차의 혼잡도별 Metering 효과분석을 시행하였으며, 그 결과 Gate Metering 시행 시 혼잡도별 승강장의 서비스 수준 및 보행밀도가 개선되는 것을 확인하였다. 승강장에서 Metering을 실시 할 경우 플랫폼 대기 공간 내 혼잡도 조절 가능성이 있다고 판단한 것 이다. 따라서, 본 연구를 통하여 철도역사 내 이용객 혼잡도 관리를 위한 정보제공 효과평가 지표 수립 및 프로그램을 통한 이용객 정보제공 효과평가 방법론 정립이 가능하다는 것으로 판단되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• 반도체디스플레이기술학회지
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• 제13권4호
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• pp.55-58
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• 2014

The next-generation AlGaN/GaN HEMT power devices need higher power at higher frequencies. To know the device characteristics, the simulation of those devices are made. This paper presents a simulation study on the DC and RF characteristics of AlGaN/GaN HEMT power devices. According to the reduction of gate length from $2.0{\mu}m$ to $0.1{\mu}m$, the simulation results show that the drain current at zero gate voltage increases, the gate capacitance decreases, and the maximum transconductance increases, and thus the cutoff frequency and the maximum oscillation frequency increase. The maximum oscillation frequency maintains higher than the cutoff frequency, which means that the devices are useful for power devices at very high frequencies.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.272-278
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• 2008

This paper investigated the a-si:H gate driver with the stepwise gate signal. In 1-chip type mobile LCD application the stepwise gate signal for low power consumption can be used by adding simple switching circuit. The power consumption of the a-Si:H gate driver can be decreased by employing the stepwise gate signal in the conventional circuit. In conventional one, the effect of stepwise gate signal can decrease slew rate and increase the fluctuation of gate-off state voltage, In order to increase the slew rate and decrease the gate off state fluctuation, we proposed a new a-Si:H TFT gate driver circuit. The simulation data of the new circuit show that the slew rate and the gate-off state fluctuation are improved, so the circuit can work reliably.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제8권3호
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• pp.57-64
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• 2019

본 논문에서는 이벤트구동 게이트수준 타이밍 시뮬레이션의 성능 향상 및 디버깅 효율성 크게 높일 수 있는 공간적 부분시뮬레이션 전략이 적용된 효율적인 예측기반 병렬 시뮬레이션 기법을 제안한다. 제안된 기법은 병렬 이벤트구동 로컬시뮬레이션들의 입력값과 출력값에 대한 빠르면서도 정확한 예측을 달성하기 위해서, 공간적 부분시뮬레이션 전략을 추상화 상위수준 시뮬레이션에 적용하여 정확한 예측 데이터를 빠르고 즉각적으로 생성해낸다. 공간적 부분시뮬레이션 전략이 적용된 예측기반 병렬 게이트수준 타이밍 시뮬레이션은 성능 평가를 위하여 사용된 6개의 벤치마크 설계들에 대하여 제일 일반적인 순차 이벤트구동 게이트수준 타이밍 시뮬레이션에 비하여 평균 약 3.7배, 상용화된 멀티코어 기반의 병렬 이벤트구동 게이트수준 타이밍 시뮬레이션에 비해서는 평균 9.7배, 그리고 기존의 가장 우수한 예측기반 병렬 이벤트구동 게이트 수준 타이밍 시뮬레이션 결과에 비해서도 평균 2.7배의 시뮬레이션 성능이 향상됨을 확인할 수 있었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• 한국진공학회지
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• 제5권2호
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.