• Journal of the Institute of Electronics Engineers of Korea SC
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• 제44권6호
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• 제13권1호
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• pp.107-113
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• 1995

Generally, the objectives of the geodetic network adjustments are for solving the configuration of geodetic net-works and the problem of observation plans. In this study, assuming that the configuration is fixed, for improving the accuracy of geodetic networks, we focus on choosing adjustment control points and adjustment methods. By choosing adjustment control points and adjustment methods, the adjustment result accuracy of national geodetic networks can be different. So, in this study, we introduce the algorithm that use free network adjustment concept to minimize the displacements of new station points but fixing existing control points. Then, us-ing adjustment results, we can check the errors of existing control points. After checking the errors of existing control point, in case of severe error points in existing control points, we change those points into unknown station points and repeat the algorithm to optimize the coordinates of new station points. As applying this algorithm to simulation network, we can check the errors of existing control points. And changing severe error points into unknown station points, we can decrease the errors of network and optimize the coordinates of new station points. From the results of simulation network adjustment, we think that, as applying this algorithms to sequential adjustment of geodetic network and public surveying that using national geodetic network, the accuracy of network adjustments can be improved.

• The Journal of the Acoustical Society of Korea
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• 제19권2호
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• pp.101-105
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• 2000

A telegram has been used to transmit the emergency news or celebration message. So, it has been very important media in our life. Although the telegram processing is more and more convenient, on the other hand, the telegram service contains only text message. The voice telegram is that delivering user's voice with text message. So, the voice telegram can be delivered sender's emotions and feelings. However, since voice information contains lots of data, large memory size and high cost processor are needed to deliver itself. In this paper, we proposed a new speech waveform coding method that has low complexity and low cost implementation for the voice telegram system. First, we fixed one basic speech waveform per pitch period and measured the waveform similarity between basic and neighbor speech waveform. Second, if the similarity satisfied threshold values, we compress the neighbor speech waveform with pitch and magnitude value per pitch period and if not, we save speech waveform. When the compression is about 45%, we obtained about 4 point in MOS.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제14권3호
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• pp.49-58
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• 2000

This paper deals with a systematic approach to neural network controller design for static VAR compensator (SVC) using a learning algorithm of error back propagation that accepts error and change of error as inputs, the momentum learning technique is used for reduction of learning time, to improve system stability. A SVC, one of the Flexible AC Transmission System(FACTS), constructed by a fixed capacitor(FC) and a thyristor controlled reactor(TCR), is designed and implemented to improve the damping of a synchronous generator, as well as controlling the system voltage.TO verify the robustness of the proposed method, we considered the dynamic response of generator rotor angle deviation, angular velocity deviation and generator terminal voltage by applying a power fluctuation and rotor angle fluctuation in initial point when heavy load and normal load. Thus, we prove the usefulness of proposed method to improve the stability of single machine-infinite bus with SVC system.

• Journal of the Korean Society of Marine Environment & Safety
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• 제18권3호
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• pp.221-226
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• 2012

This research presents an analysis of algorithm for ship track-keeping along a given trajectory. The maneuver of a free running model ship guiding through a simple path are presented. In order to solve the above problem, a desired trajectory is usually determined by GPS points in a pre-fixed place then these points are set in a pre-programmed navigation so that the ship would be automatically tracked. Proportional-Derivative(PD) control which is useful for fast response controllers was used in this program as a course keeping system. A high accuracy GPS receiver was installed on the model ship that could provide positions frequently, the system will compare and give out the remaining distance and heading to the target way-point. The results of ship auto track-keeping experiment will be explained in order to illustrate the adjustment in controlling parameters. These results can be utilized as a preliminary step to carry out the experiment of ship collision avoidance system and automatic berthing in the future.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• 제38권3호
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• pp.221-227
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• 2010

Recent development in seeker technology explores a new seeker design in which, with larger field-of-view (FOV), optical parts are strapped down to a body (hence, called as a body-fixed seeker or a strapdown seeker). This design has several advantages such as comparatively easier maintenance and calibration by removing complex mechanical moving parts, increasing reliability, and cost savings. On the other hand, the strapdown seeker involves difficulties in implementing guidance laws since it does not directly provide inertial LOS rates. Instead, information for generating guidance commands should be extracted by estimating missile/target relative motion utilizing target images on the image plane of a strapdown seeker. In this research, a new framework based on an unscented Kalman filter is developed for estimating missile/target relative motion on the simplified assumption of a point source target. Performance of a terminal guidance algorithm, in which guidance command is generated based on the estimated relative motion, is demonstrated by a missile/target engagement simulation.

• Journal of IKEEE
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• 제20권4호
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• pp.398-411
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• 2016

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.

• The Journal of the Acoustical Society of Korea
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• 제23권5호
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• pp.420-427
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• 2004

This paper presents real time implementation of 4kbps EHSX (Enhanced Harmonic Stochastic Excitation) speech coder that combines the harmonic vector excitation coding with time-separated transition coding. The harmonic vector excitation coding uses the harmonic excitation coding for voiced frames and used the vector excitation coding with the structure of analysis-by-synthesis for unvoiced frames, respectively. For transition frames mixed with voiced and unvoiced signal, we use the time-separated transition coding. In this paper. we present the optimization methods of implementation speech coder on the EMS320C6701/sup (R)/ DSP. To reduce the complex for real-time implementation. we perform the optimization method in algorithm by replacing the complex sinusoidal synthesis method with IFFT. and we apply fully pipelines hand assembly coding after converting it from floating source to fixed source. To generate a more efficient code. we also make use or the available EMS320C6701/sup (R)/ resources such as Fastest67x library and memory organization.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제29권9C호
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• pp.1337-1344
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• 2004

This paper deals with analysis and real-time Implementation of a wide band adaptive multirate speech codec (AMR-WB) using a fixed-point DSP of TI's TMS320C6201. In the AMR-WB codec, input speech is divided into two frequency bands, lower and upper bands, and processed independently. The lower band signal is encoded based on the ACELP algorithm and the upper band signal is processed using the random excitation with a linear prediction synthesis filter. The implemented AMR-WB system used 218 kbytes of program memory and 92 kbytes of data memory. And its proper operation was confirmed by comparing a decoded speech signal sample-by-sample with that of PC-based simulation. Maximum required time of 5 75 ms for processing a frame of 20 ms of speech validates real-time operation of the Implemented system.

• Journal of Biomedical Engineering Research
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• 제18권4호
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.