• Progress in Superconductivity
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• v.3 no.2
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• pp.172-177
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• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.2
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• pp.93-101
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• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.112-115
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• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.30-37
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• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1963-1964
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• 2008

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. We propose a new technique to re-design about clock operation. This technique propose about low power operation of scan clock and saved time of test operation.

• Progress in Superconductivity
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• v.4 no.1
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• pp.37-41
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• 2002

In this work. we have designed two different kinds of Rapid Single Flux Quantum (RSFQ) OR-gates. One was based on the already developed RSFQ cells and the other was aimed to develop a more compact version. In the first circuit, we used a combination of two D Flip-Flops and a merger and in the other circuit we used a combination of RS Flip-Flops and Confluence Buffer. We tested the circuit performance by using the simulation tools, Xic and Wrspice. We obtained the operation margins of the circuit elements by a margin calculation program, and we obtained the minimum operation margins of $\pm$30%. The circuits were laid out, aimed to fabricate by using the existing KRISS Nb process. KRISS Nb process includes the $Nb／Al_2$$O_3$／Nb trilayer fabricated by DC magnetron sputtering and the reactive ion etching technique for the definition of the features. The major tools used in the layouts were Xic and L-meter.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.2
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• pp.24-27
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• 1975

A Synthesis method for multiple-input change transition-sensitive asynchronous sequential circuits is proposed. Both internal states and output states are synthesized from primitive flow tables. It is Btown that cur realization is faster than that of Chuang's. It is pointed out that Chuang's realization of output states contains malfunctions. In this paper, output stales are easily realized from primitive flaw table by the method of controlled excitation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.