• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.73-74
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• 2006

Ferroelectric thin films have been widely investigated for future nonvolatile memory application. We fabricated the BLT ($(Bi,La)_4Ti_3O_{12}$) films on Si using a STA ($SrTa_2O_6$) buffer layer BLT and STA film were prepared by sol-gel method. Measurement data by XRD and AFM, showed that BLT film and STA films were well crystallized and a good surface morphology. From C-V measurement reward that the Au/BLT/STA/Si structure showed a clockwise hysteresis loop with a memory window of 1.5 V for the bias voltage sweep of ${\pm}5$ V. From results, the Au/BLT/STA/Si structure is useful for FeFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.77-78
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• 2009

We report numerical simulations to investigate of the dependence of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of 10um, but varying the channel width W from 5nm to 5um, and thickness t from 10nm to 30nm. We have shown that $Q_{ON}/Q_{OFF}$ drastically decreases (from ${\sim}2.9{\times}10^4$ to ${\sim}9.8{\times}10^3$) as the channel thickness increases (from 10nm to 30nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed than that in the bottom of control channel.

• Macromolecular Research
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• v.17 no.9
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• pp.646-650
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• 2009

We report the fabrication of pentacene organic field-effect transistors (OFETs) using a fluorinated styrene-alt-maleic anhydride copolymer gate dielectric, which was prepared from styrene derivatives with a fluorinated side chain [$-CH_2-O-(CH_2)_2-(CF_2)_5CF_3$] and maleic anhydride through a solution polymerization technique. The fluorinated side chain was used to impart hydrophobicity to the surface of the gate dielectric and maleic anhydride was employed to improve its wetting properties. A field-effect mobility of 0.12 cm$^2$/Vs was obtained from the as-prepared top-contact pentacene FETs. Since various functional groups can be introduced into the copolymer due to the nature of maleic anhydride, its physical properties can be manipulated easily. Using this type of copolymer, the performance of organic FETs can be enhanced through optimization of the interfacial properties between the gate dielectric and organic semiconductor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.728-731
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• 2009

We report numerical simulations to investigate of the dependendce of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of $10\;{\mu}m$, but varying the channel width W from 5 nm to $5\;{\mu}m$, and thickness t from 10 nm to 30 nm. We have show that $Q_{ON}/Q_{OFF}$ drastically decreases (from $^{\sim}2.9{\times}10^4$ to $^{\sim}9.8{\times}10^3$) as the channel thickness increases (from 10 nm to 30 nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed then in the bottom of control channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.920-927
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• 1994

A development of an efficient 14.0~14.5GHz 3 Watt SSPA is described in this paper, which is applicable to the very small aperture terminal(VSAT) for bidirectional data and voice signal transmission in low cost and with small size. The SSPA consists of two stages of low noise amplifiers using the low noise GaAs FETs. two stages of medium power amplifiers using the medium power GaAs FETs, and three stages of power amplifiers including a balanced amplifier using an internally matched power GaAs FET. The achieved with this seven stage amplifiers are 42dB signal power gain, 7dB noise figure, 35dBm output power at 1dB gain compression point and 2.0 and 1.5 input and output VSWR respectively.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1339-1340
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• 2007

본 연구에서는 이종 차원 나노선과 나노입자의 결합에 따른 단일 나노선 소자의 전기적 특성 및 메모리 효과를 연구하였다. 열증착법으로 성장 된 p 형 Si 나노선에 Atomic Layer Deposition (ALD) 방법으로 10nm의 $Al_{2}O_{3}$를 증착한 후 Low Precensure - Chemical Vapor Deposition (LP-CVD)를 이용하여 Polycrystalline Sicon(Poly-Si)을 Si 나노선 위에 5nm 증착하고 습식 에칭법을 이용하여 poly Si 내의 $SiO_x$를 제거하여 Si 나노입자를 Si 나노선 위에 형성시켰다. 그 후 포토리소그래피 공정을 이용하여 Top gate 형태의 나노선-나노입자 이종결합 Field-Effect Transistor (FET) 소자를 제작하여 게이트 전압에 따른 드레인 전류-전압($I_{DS}-V_{DS}$)의 변화를 측정하여 나노선의 전기 소자로서의 특성을 확인하고, 게이트 전압을 양방향으로 swing 하면서 인가하여 $I_{DS}$ 전류 특성이 변화하는 것을 통해 메모리 효과를 조사하였다. 또한 나노입자의 결합이 게이트 전압의 인가 시간에 따라 드레인 전류에 영향을 미치는 것을 확인하여 메모리 소자로서의 가능성을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.84-84
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• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.5
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• pp.348-356
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• 2021

Field-effect transistors (FETs) are the key elements of conventional electronics; hence, have drawn a lot of research and commercial interests. In recent years, metal halide perovskite materials have achieved a remarkable efficiency of 29.15% in the field of photovoltaics, and have drawn the scientific community's attention to promote their use in the field of optoelectronics, such as FETs and phototransistors. The MAPbI₃ (methylammonium lead iodide) perovskite TFT has achieved a record hole mobility of 21.41 cm²/V-s in the year 2020. In this review, we will briefly discuss the physical structure of MAPbI₃ perovskite and the essential factors that stimulate these devices, together with the role of defects, the ion migration concept, and the implication of both dielectric and electrode materials on the device's performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.28-34
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• 2011

In previous reports, we investigated a selective assembly method of fabricating single-walled carbon nanotubes (SWCNTs) on a silicon-dioxide ($SiO_2$) surface by using only a photolithographic process. In this paper, we have fabricated field effect transistors (FETs) with SWCNT channels by using the technique mentioned above. Also, we have electrically measured gating effects of these FETs under different source-drain voltages ($V_{SD}$). These FETs have been fabricated for sensor applications. Photoresist (PR) patterns have been made on a $SiO_2$-grown silicon (Si) substrate by using a photolithographic process. This PR-patterned substrate have been dipped into a SWCNT solution dispersed in dichlorobenzene (DCB). These PR patterns have been removed by using aceton. As a result, a selectively-assembled SWCNT channels in FET arrays have been obtained between source and drain electrodes. Finally, we have successfully fabricated 4 FET arrays based on SWCNT-channels by using our simple self-assembly technique.