• 조명전기설비학회논문지
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• 제22권8호
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• pp.52-58
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• 2008

본 논문에서는 2.4[GHz]/5.8[GHz] 대역의 이중대역 스위치 설계에 대하여 논한다. 이 스위치는 TDD시스템에 적용 가능하며, 광대역 특성을 개선할 수 있는 새로운 구조를 제안하고 시뮬레이션을 통해 최적의 구조로 설계하였다. 2.4[GHz]/5.8[GHz] 이중대역 스위치는 현재 상용화되고 있는 802.11a/b/g 시스템에 응용할 수 있는 광대역, 고출력, 높은 격리도를 갖는 구조를 연구하였다. 스위치의 송신부는 2개의 FET를 스택 구조로 병렬 스위칭 소자로 동작하도록 설계하였다. 수신부는 기본적인 직/병렬 FET에 추가로 직렬 FET를 삽입한 비대칭 구조를 갖도록 수신부를 설계하였다. SPDT(Single Pole Double Throw) Tx/Rx FET 스위치는 하나의 입력에 2개의 출력으로 스위칭할 수 있는 장치이다. 이 제작된 스위치는 삽입손실 특성은 DC$\sim$6[GHz]까지 3[dB]보다 낮으며 수신경로의 격리도는 -30[dB]이하의 특성을 가지고 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.548-551
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• 2007

최근에 유기물 전계효과 트랜지스터의 연구는 전자 소자 분야에서 널리 알려져 있다. 특히 본 연구에서는 CuPc 물질을 기본으로 하여 소자를 제작하고, 또한 기판의 온도를 달리 하여 제작하였다. CuPc FET 소자는 top-contact 방식으로 제작하였으며, 기판의 온도는 상온과 $150^{\circ}C$로 달리 하였다. 또한 CuPc의 두께는 40nm로 하였고, 채널의 길이는 $50{\mu}m$, 폭은 3mm로 하였다. 제작된 소자를 이용하여 전압-전류 특성을 측정하였다.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• 한국표면공학회지
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• 제41권1호
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• pp.12-15
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• 2008

The zinc oxide(ZnO) nanowires were deposited on Si(001) substrates by thermal chemical vapour deposition without any catalysts. SEM data suggested that the grown nanostructures were the well-aligned ZnO single crystals with preferential orientation. Back-gate ZnO nanowire field effect transistors(FET) were successfully fabricated using a photolithography process. The fabricated nanowire FET exhibits good contact between the ZnO nonowire and Au metal electrodes. Based on I-V characteristics it was found out that the ZnO nanowire revealed a characteristic of n-type field effect transistor. The drain current increases with increasing drain voltage, and the slopes of the $I_{ds}-V_{ds}$ curves are dependent on the gate voltage.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.115-115
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• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The Power MOSFET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 40 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}\;cm^{-3}$, size of $600\;{\mu}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50\;{\mu}A$. We offer the layout of the proposed Power MOSFET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• Bulletin of the Korean Chemical Society
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• 제34권4호
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• pp.1035-1038
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• 2013

Rolling circle amplification (RCA) of DNA on an aligned-carbon nanotube (a-CNT) surface was electrically interfaced by the a-CNT based filed effect transistor (FET). Since the electric conductance of the a-CNT will be dependent upon its local electric environment, the electric conductance of the FET is expected to give a very distinctive signature of the surface reaction along with this isothermal DNA amplification of the RCA. The a-CNT was initially grown on the quartz wafer with the patterned catalyst by chemical vapor deposition and transferred onto a flexible substrate after the formation of electrodes. After immobilization of a primer DNA, the rolling circle amplification was induced on chip with the a-CNT based FET device. The electric conductance showed a quite rapid increase at the early stage of the surface reaction and then the rate of increase was attenuated to reach a saturated stage of conductance change. It took about an hour to get the conductance saturation from the start of the conductance change. Atomic force microscopy was used as a complementary tool to support the successful amplification of DNA on the device surface. We hope that our results contribute to the efforts in the realization of a reliable nanodevice-based measurement of biologically or clinically important molecules.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.486-486
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• 2013

Silicon nanowire devices fabricated by bottom-up methods are attracted due to their electrical, mechanical, and optical properties. Especially, to functionalize the surface of silicon nanowires by molecules has received interests. The changes in the characteristics of the molecules is delivered directly to the surface of the silicon nanowires so that the silicon nanowire can be utilized as an efficient read-out device by using the electronic state change of molecules. The surface treatment of the silicon nanowire with light-sensitive molecules can change its optical characteristics greatly. In this paper, we present the optical response of a SiNW field-effect-transistor (FET) conjugated with porphyrin molecules. We fabricated a SiNW FET and performed porphyrin conjugation on its surface. The characteristic and the optical response of the device shows a large difference after conjugation while there is not much change of the surface in the SEM observation. It attributed to the existence of few layer porphyrin molecules on the SiNW surface and efficient variation of the surface potential of the SiNW due to light irradiation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.9-11
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• 2000

To increase the device linearities and the breakdown-voltages of FETs, Al$\sub$0.25/ Ga$\sub$0.75/AS / In$\sub$0.25/Ga$\sub$0.75/As / Partially doped channel FET(DCFET) structures are proposed. The metal- insulator -semiconductor (MIS) like structures show the high gate-drain breakdown voltage(-20 V) and high linearities. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range.