Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Fabrication of SOI FinFET Devices using Arsenic Solid-phase-diffusion

  • Cho, Won-Ju (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Koo, Hyun-Mo (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Lee, Woo-Hyun (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Koo, Sang-Mo (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Chung, Hong-Bay (Department of Electronic Materials Engineering, Kwangwoon University)
  • Published : 2007.05.01
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Abstract

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

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References

  1. N. Miura, Y. Abe, K. Sughihara, T. Oishi, T. Furukawa, T. Nakahata, K. Shiozawa, S. Maruno, and Y. Tokuda, 'Junction capacitance reduction due to self-aligned pocket implantation m elevated source/drain NMOSFETs', IEEE Trans. Elec. Dev., Vol. 48, No. 9, p. 1969, 2001 https://doi.org/10.1109/16.944184
  2. E. Gili, V. D. Kunz, C. H. de Groot, T. Uchino, D. Donaghy, S. Hall, and P. Ashburn, 'Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance', 33rd Conference on European Solid-State Device Research, p. 533, 2003
  3. J. R. Pfiester, R. D. Sivan, H. Ming Liaw, C. A. Seelbach, and C. D. Gunderson, 'A self-aligned elevated source/drain MOSFET', IEEE Electron Dev. Lett., Vol. 11, No. 11, p. 365, 1990 https://doi.org/10.1109/55.62957
  4. D. J. Frank, S. E. Laux, and M. V. Fishchetti, 'Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?', Technical Digest of International Electron Device Meeting, p. 553, 1992
  5. H. S. Wong, K. K. Chan, and Y. Taur, 'Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel', Technical Digest of International Electron Device Meeting, p. 427, 1997
  6. H. S. Wong, D. J. Frank, and P. M. Solomon, 'Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOl MOSFET's at the 25 nm channel length generation', Technical Digest of International Electron Device Meeting, p. 407, 1998
  7. D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Cuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, 'FinFET-a self-aligned double-gate MOS FET scalable to 20 nm', IEEE Trans. Electron Devices, Vol. 47, No. 12, p. 2320, 2000 https://doi.org/10.1109/16.887014
  8. Y. K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T. J. King, J. Bokor, and C. Hu, 'Sub-20 nm CMOS FinFET technologies', Technical Digest of International Electron Device Meeting, p. 19.1.1, 2001
  9. W. J. Cho, J. H. Yang, K. J. Im, J H Oh, and S. J. Lee, 'Fabrication and process simulation of sal MOSFETs with a 30-nm gate length', J Korean Phys. Soc., Vol. 43, No.5, p. 892, 2003 https://doi.org/10.3938/jkps.43.892