• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.454-457
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• 2010

The influence of CuO addition on what of the $(Ba,Sr)TiO_3$ ceramics was studied. The sintering temperature of $(Ba,Sr)TiO_3$ ceramics was lowered by the addition of CuO additives. The 1 - 5 wt% CuO were selected and employed as the sintering aids. Low-Temperature Co-fired Ceramic technologies are popular technologies used in the manufacture of microwave devices. In this study, crystalline and electrical properties of CuO doped $(Ba,Sr)TiO_3$ ceramics were investigated to determine the low temperature sintering properties. The addition of CuO to $(Ba,Sr)TiO_3$ lowered the sintering temperature from $1350^{\circ}C$ to $1150^{\circ}C$. The dependence of the sintering temperature shrinkage rate and mechanism of CuO doped $(Ba,Sr)TiO_3$ ceramics are investigated and discussed. Also, the crystalline structure of CuO - doped $(Ba,Sr)TiO_3$ ceramics is discussed by the X-ray diffraction (XRD) method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.4
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• pp.203-208
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• 2014

In this study, Sputtering method was used to grow Al-dopes ZnO films on a CIGS absorber layer, in order to examine the effect of TCO on properties of CIGS solar cell devices. Structural, electrical and optical properties were investigated by varied thickness of Al-dopes ZnO films. Also, relation to the application as a window layer in CIGS thin film solar cell were studied. It was found that the electrical and structural properties of ZnO:Al film improved with increasing its thickness. However, the optical properties degraded. Jsc of the fabricated CIGS based solar cells was significantly influenced by the variation of the ZnO:Al window layer thickness. Because ZnO:Al window layer is one of the Rs factors in CIGS solar cell. Rs has the biggest influence on efficiency characteristic. In order to obtain high efficiency of CIGS solar cell, ZnO:Al window layer should be fabricated with electrically and optically optimized.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

• Journal of IKEEE
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• v.22 no.3
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• pp.870-873
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• 2018

This paper presents the high frequency resonant inverter using ZVS(Zero Voltage Switching) known as the soft switching technology, which can reduce the turn-on and turn-off switching losses. Also, the analysis of the proposed resonant inverter is described by adopting normalized parameters, and its operating characteristics are evaluated according to the switching frequency and parameters. An example of 1.3[kW] IH-Jar design technique is presented based on the characteristic values obtained from the theoretical analysis. To prove the validity of the theoretical analysis, the experimental results using IGBT as the switching devices are additionally presented. In the future, it can be practically used in various power systems such as induction heating cooking, IH-Jar etc.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1481-1500
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• 2016

Device-to-Device (D2D) communication underlaying macro-small cell networks, as one of the promising technologies in the era of 5G, is able to improve spectral efficiency and increase system capacity. In this paper, we model the cross- and co-tier D2D communications in two-tier macro-small cell networks. To avoid the complicated interference for cross-tier D2D, we propose a mode selection scheme with a dedicated resource sharing strategy. For co-tier D2D, we formulate a joint optimization problem of power control and resource reuse with the aim of maximizing the overall outage capacity. To solve this non-convex optimization problem, we devise a heuristic algorithm to obtain a suboptimal solution and reduce the computational complexity. System-level simulations demonstrate the effectiveness of the proposed method, which can provide enhanced system performance and guarantee the quality-of-service (QoS) of all devices in two-tier macro-small cell networks. In addition, our study reveals the high potential of introducing cross- and co-tier D2D in small cell networks: i) cross-tier D2D obtains better performance at low and medium small cell densities than co-tier D2D, and ii) co-tier D2D achieves a steady performance improvement with the increase of small cell density.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.6
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• pp.1-7
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• 2008

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35\;{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.878-881
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel thickness and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.191-191
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• 2007

유효 산화막 두께가 약 2.0nm 정도의 $ZrO_2$ 절연막 위에 Ta-Mo 금속 합금과 Ru-Zr 금속 합금을 Co-sputtering 방법을 이용하여 여러 가지 일함수를 갖는 MOS capacitor를 제작하여 전기적 재료적 특성에 관하여 연구를 하였다. 그 결과 각각의 금속 합금 게이트는 4.1eV 에서 5.1eV 사이의 다양한 일함수를 나타냈으며, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$, $700^{\circ}C$, $800^{\circ}C$ RTA 후의 C-V특성 곡선 및 I-V 측정을 통하여 누설전류를 확인하였다. 그 결과 Ta-Mo 금속 합금의 경우 스퍼터링 파워가 100W/70W에서 NMOS에 적합한 일함수를 가졌으며, Ru-Zr 금속 합금의 경우 스퍼터링 파워가 50W/100W에서 NMOS에 적합한 일함수를 가졌다. 열처리 후의 C-V특성 곡선에서도 정전용랑 값이 거의 변하지 않았으며 평탄 전압의 변화도 거의 없었다. 누설전류 특성에서는 물리적 두께가 비슷한 기존의 $SiO_2$ 절연막에서 실험결과와 비교하여 약 100배 정도 감소되었음을 알 수 있었다. 또한 기존의 실험들에서 나타난 열처리 후의 $ZrO_2$ 절연막과 Si 기판 사이의 Interfacial layer 의 동반 두께 증가로 인한 전기적 특성 저하가 나타나지 않는 줄은 특성을 보여준다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.732-741
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• 2018

In order to maximize the usable capacity of a BMS (battery management system) that uses several battery cells connected in series, a cell balancing technique that equips each cell with the same voltage is needed. In the active cell balancing circuit using a multi-winding transformer, a balancing circuit that transfers energy directly to the cell (cell-to-cell) is composed of a PMOS switch and a gate driving chip for driving the NMOS switch. The TLP2748 photocoupler and the TLP2745 photocoupler are required, resulting in increased cost and reduced integration. In this paper, instead of driving PMOS and NMOS switching devices by using photocoupler, we proposed 70V BCD process based PMOS gate driving circuit, NMOS gate driving circuit, PMOS gate driving circuit and NMOS gate driving circuit with improved switching time. ${\Delta}t$ of the PMOS gate drive switch with improved switching time was 8.9 ns and ${\Delta}t$ of the NMOS gate drive switch was 9.9 ns.