• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권9호
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• pp.438-443
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• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• E2M - 전기 전자와 첨단 소재
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• 제11권10호
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• pp.72-77
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• 1998

The effects of Al micro-bumps on the magnetic properties of CoCr(Pt)Ta/Cr films deposited on glass substrates were investigated. The coercivity increased and the coercivity squareness decreased by incorporating Cr/Al underlayers. The cause of the coercivity increase is attributed to the reduction of Co(0002) texture, the increase of magnetic isolation of CoCr(Pt)/Ta grains, and the refinement of CoCr(Pt)/Ta grains deposited on Cr/Al underlayers. The effects of an Al overlayer on the magnetic properties of CoCr(Pt)Ta/Cr films were also studied. The decrease of coercivity squareness is ascribed to the magnetic isolation of CoCr(Pt)Ta grains.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• 전기학회논문지
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• 제66권4호
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• pp.636-642
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• 2017

Recently, new power devices, SiC and GaN FETs, are commercialized. They are expected to change power electronics environments. They will raise operating frequencies of power electronic equipments. Accordingly, design method will be changed greatly. In this paper, an 1 MHz resonant converter with fully compensated coreless isolation transformer is proposed, where the primary voltage is proportional to the secondary current and the primary current to the secondary voltage. 30 W prototype is constructed and tested, and its usefulness is verified.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권10호
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• pp.575-582
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• 2003

A new FDOs (fault diagnostic observers) and the residual generation schemes using the FDOs are suggested for the process fault detection and isolation of linear (control) systems. The design method of the FDO is described, first, for the full measurement systems. Then it is extended for the systems with unmeasurable state variables. An unknown input observer is proposed and applied for the extension. The size of the observer bank may be the smallest, specially in full measurement systems, because the order of the proposed FDO is very low. In spite of the simplicity, the scheme provides the same information for the detection and isolation of the anticipated faults as the conventional multiple observer based schemes. The residuals may be structured so that fault isolation can be performed by pre-selected logic. An FDIS using the proposed scheme is constructed for the model of the four-tank system. Simulation results show the practical feasibility of the proposed scheme.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권10호
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• pp.683-692
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• 2000

A new primary-side-assisted zero-voltage and zero-current switching full bridge DC-DC converter with transformer isolation is proposed. The auxiliary circuit adopted to assist ZCS for the leading leg is composed of only one small transformer and two diodes. It has a simple and robust structure, and load current control capability even in short circuit conditions. Possibility of magnetic saturation due to asymmetricity of circuits or transient phenomena is greatly reduced, which is a very attractive feature in DC/DC converters with transformer isolation. The power rating of the auxiliary transformer is about 10% of that of the main transformer. Operation of a 12.5KW prototype designed for welding application was verified by experiments.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.501-504
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• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• 대한전기학회논문지:전력기술부문A
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• 제48권3호
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• pp.257-262
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• 1999

This paper proposes a composite fault detection and isolation method by combining the parameter estimation method[1] with the observer-based method[2] to take advantages of both methods. Some properties of the parameter estimation method and the observer-based method are revieved, and the composite algorithm is presented. To exemplify the performance of the method proposed, some simulations applied to remotely piloted vehicle are performed.

• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.647-655
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• 2003

Commonly used SAW duplexers have a difficulty on manufacture so that a transmission line is printed on the package or an LTCC multi-layer is needed because a quarter-wave transmission line which is a kind of an isolation network is applied to the SAW duplexers. In this study, new structures of one chip type SAW duplexers are proposed. In the proposed structure, Tx and Rx SAW ladder filters and isolation networks are located on a single 36LiTaO$_3$ piezoelectric substrate. The manufacture process is very simple than commonly used product. It is possible to improve tile performance by means of optimizing the micro-strip line lumped elements. It is easy to integrate and modulate with other surrounding components. The optimal design techniques can be applied to other kind of multi-port devices.