• 제목/요약/키워드: Efficient implementation

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A Multithreaded Implementation of HEVC Intra Prediction Algorithm for a Photovoltaic Monitoring System

  • Choi, Yung-Ho;Ahn, Hyung-Keun
    • Transactions on Electrical and Electronic Materials
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    • 제13권5호
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    • pp.256-261
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    • 2012
  • Recently, many photovoltaic systems (PV systems) including solar parks and PV farms have been built to prepare for the post fossil fuel era. To investigate the degradation process of the PV systems and thus, efficiently operate PV systems, there is a need to visually monitor PV systems in the range of infrared ray through the Internet. For efficient visual monitoring, this paper explores a multithreaded implementation of a recently developed HEVC standard whose compression efficiency is almost two times higher than H.264. For an efficient parallel implementation under a meshbased 64 multicore system, this work takes into account various design choices which can solve potential problems of a two-dimensional interconnects-based 64 multicore system. These problems may have not occurred in a small-scale multicore system based on a simple bus network. Through extensive evaluation, this paper shows that, for an efficient multithreaded implementation of HEVC intra prediction in a mesh-based multicore system, much effort needs to be made to optimize communications among processing cores. Thus, this work provides three design choices regarding communications, i.e., main thread core location, cache home policy, and maximum coding unit size. These design choices are shown to improve the overall parallel performance of the HEVC intra prediction algorithm by up to 42%, achieving a 7 times higher speed-up.

Word-Based FCSRs with Fast Software Implementations

  • Lee, Dong-Hoon;Park, Sang-Woo
    • Journal of Communications and Networks
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    • 제13권1호
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    • pp.1-5
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    • 2011
  • Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.

Spread Specturm 방식을 이용한 무선 LAN MODEM의 구현 (On the implementation of spectrum MODEM for wireless LAN)

  • 심복태;박종현;박흥직;김제우;김관옥
    • 전자공학회논문지A
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    • 제32A권1호
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    • pp.1-13
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    • 1995
  • In this paper, a specification for wireless LAN MODEM using direct sequence spread spectrum (DS/SS) technique is presented. Some algorithms and hardware architectures for an efficient implementation of the DS/SS MODEM are suggested. In the method, all baseband signal processing are done digitally for single chip implementation. Schemes of DQPSK baseband modulation/demodulation, despreading with digital matched filter, digital timing recovery, and efficient carrier sensing are among the discussed algorithms. We also performed various kinds of simulations to evaluate the system performance and to extract parameters for hardware implementation. In addition, the pictorial view of ASIC of the SS MODEM is also shown.

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센서 네트워크 상에서의 HUMMINGBIRD2 암호화 속도 최적화 구현기법 (A Speed Optimized Implementation Technique of HUMMINGBIRD2 Encryption over Sensor Network)

  • 서화정;김호원
    • 한국통신학회논문지
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    • 제37권6B호
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    • pp.414-422
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    • 2012
  • 본 논문에서는 초경량 대칭키 암호화 기법인 HUMMINGBIRD2 알고리즘을 센서 모트상에서의 최적화 구현기법을 제시한다. 효율적인 구현을 위해 센서보드상에 제공되는 레지스터의 활용을 극대화하며 최적화된 주소접근 기법을 적용하여 암복호화에 소요되는 시간을 최소화하였다. 해당 대칭키 암호화 구현기법을 통해 자원 한정적인 센서 상에서의 안전하고 효율적인 보안 통신이 가능하도록 한다.

Computationally Efficient Implementation of a Hamming Code Decoder Using Graphics Processing Unit

  • Islam, Md Shohidul;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of Communications and Networks
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    • 제17권2호
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    • pp.198-202
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    • 2015
  • This paper presents a computationally efficient implementation of a Hamming code decoder on a graphics processing unit (GPU) to support real-time software-defined radio, which is a software alternative for realizing wireless communication. The Hamming code algorithm is challenging to parallelize effectively on a GPU because it works on sparsely located data items with several conditional statements, leading to non-coalesced, long latency, global memory access, and huge thread divergence. To address these issues, we propose an optimized implementation of the Hamming code on the GPU to exploit the higher parallelism inherent in the algorithm. Experimental results using a compute unified device architecture (CUDA)-enabled NVIDIA GeForce GTX 560, including 335 cores, revealed that the proposed approach achieved a 99x speedup versus the equivalent CPU-based implementation.

비정렬 격자계에서 강건하고 효율적인 LU-SGS 기법 개발: Part Ⅱ- 효율적인 적용 (Robust and Efficient LU-SGS Scheme on Unstructured Meshes: Part Ⅱ - Efficient Implementation)

  • 김주성;권오준
    • 한국전산유체공학회지
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    • 제9권3호
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    • pp.39-48
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    • 2004
  • In the present study, an efficient implementation technique of the van Leer's implicit operator is suggested in accordance with the Roe's explicit operator. By using an efficient treatment of the off-diagonal terms, which occupy most of the memory requirement for the linear system of equations, it is shown that the improved scheme only requires less than 30% of memory and is approximately 10-20% faster than the baseline scheme.

초마디 멀티프런탈 방법의 효율적인 구현 (An Efficient Implementation of the Supernodal Multifrontal Method)

  • 박찬규;박순달
    • 경영과학
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    • 제19권2호
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    • pp.155-168
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    • 2002
  • In this paper, some efficient implementation techniques for the multifrontal method, which can be used to compute the Cholesky factor of a symmetric positive definite matrix, are presented. In order to use the cache effect in the cache-based computer architecture, a hybrid method for factorizing a frontal matrix is considered. This hybrid method uses the column Cholesky method and the submatrix Cholesky method alternatively. Experiments show that the hybrid method speeds up the performance of the supernodal multifrontal method by 5%~10%, and it is superior to the Cholesky method in some problems with dense columns or large frontal matrices.

혼합정수계획법을 위한 분지한계법의 효율적인 구현 (An efficient implementation of branch-and-cut algorithm for mixed integer programming)

  • 도승용;이상욱;임성묵;박순달
    • 한국경영과학회:학술대회논문집
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    • 대한산업공학회/한국경영과학회 2002년도 춘계공동학술대회
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    • pp.1-8
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    • 2002
  • A Branch-and-Cut algorithm is a branch-and-bound algorithm in which rutting planes are generated throughout the branch-and-bound tree. It is now one of the most widespread and successful methods for solving mixed integer programming problems. In this paper we presents efficient implementation techniques of branch-and-cut algorithm for miked integer programming problems.

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Fast Implementation of the Progressive Edge-Growth Algorithm

  • Chen, Lin;Feng, Da-Zheng
    • ETRI Journal
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    • 제31권2호
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    • pp.240-242
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    • 2009
  • A computationally efficient implementation of the progressive edge-growth algorithm is presented. This implementation uses an array of red-black (RB) trees to manage the layered structure of check nodes and adopts a new strategy to expand the Tanner graph. The complexity analysis and the simulation results show that the proposed approach reduces the computational effort effectively. In constructing a low-density parity check code with a length of $10^4$, the RB-tree-array-based implementation takes no more 10% of the time required by the original method.

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A Survey on the Implementation of Musculoskeletal Disorders Prevention Program in Shipbuilding Industry

  • Kim, Day-Sung
    • 대한인간공학회지
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    • 제31권1호
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    • pp.151-156
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    • 2012
  • Objective: In 2010, the rate of injuries and illnesses in the shipbuilding industry was 1.20, about 1.74 times higher than the average of overall industries(0.69). Musculoskeletal disorders(MSDs) became a major problem since 2000 in shipbuilding industry. The purpose of this study was to provide efficient implementation management through evaluating the economic effectiveness of the Musculoskeletal Disorders Prevention Program(MDPP). Successfully implementing the MDPP in the workplace may decrease the risk of MSDs and therefore reduce MSDs related costs. Methods: Occupational accident index (frequency rate, severity rate, and frequency severity indicator), estimated direct costs, and total occupational accident occurrence rate were provided by analysis of MSDs, statistical analysis of MDPP decreed companies, and data analysis of implementation. Results: The study shows the number of MSDs for MDPP decreed companies decreased 76.2% from 2,319 in 2004 to 551 in 2008. Above all, the number of MSDs decreased 78.7% in Shipbuilding industries. Forty companies (85.1%) showed a decreasing tendency and 27.7% of those had an $R^2$ > 0.7. Similar results were found in severity rate and frequency severity indicator. From these results, it appears there are a number of advantages in implementing the MDPP. Conclusion: MDPP effectiveness was demonstrated by analysing implementation and occupational accident index. A more effective and efficient implementation would take into account business sector, size, policy, and organization of the company.