• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• 전기전자학회논문지
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• 제27권3호
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• pp.258-264
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• 2023

본 논문에서는 부하전류에 따라 LDO(Low Drop Out) 레귤레이터의 효과적인 동작과 파괴 방지를 위해 ESD(Electro Static Discharge) 보호회로를 내장한 LDO 레귤레이터를 제안한다. 제안하는 LDO 레귤레이터는 additional feedback current 회로구조를 이용하여 LDO 레귤레이터의 출력전압에 따라 더욱 효과적으로 패스 트랜지스터의 게이트 노드 전압을 조절할 수 있다. 또한 기존의 ESD 보호소자에 P+ bridge를 추가하여 SCR 루프 상의 전류 이득을 감소시켜 홀딩 전압을 약 2V 가량 높인 새로운 구조를 내장하여 ESD 상황에 대해 높은 신뢰성을 가질 것으로 예상된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.319-320
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• 2006

In order to improve the ESD(Electrical Static Discharge) resistance of multilayer chip varistors, we have investigated ZnO-$Pr_6O_{11}$ based chip varistor by applying tape casting technology, whose fundamental component were ZnO : $Pr_6O_{11}$ :$Co_3O_4$: $Y_2O_3$: $Al_2O_3$=93.67: 2.53:2.53:1.25 : 0.015 (wt %). The effect of sintering condition on the multilayer chip varistors and electric properties was studied. The electrical properties and ESD resistance of multilayer chip varistor could be influenced the sintering temperature and condition.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.105-109
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• 2002

A TVS and Varistor are preservative equipment against electro static discharge(ESD). We use a TVS for I/O protection of a circuit which has faster response time than a Varistor. And a Varistor has large power capability, therefore, which be used in input stage for internal pressure prevention. This paper will compare a TVS with a Varistor with respect to response characteristic to ESD in DC 24[V] low voltage circuit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 제4회 영호남학술대회 논문집
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• pp.19-24
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• 2002

Static electricity is an everyday phenomenon. There can be few of us who have not experienced a static shock after sliding across a car seat. Other static nuisance effects include the cling of some fabrics to the body, the sticking of a plastic document cover, or the attraction of dust to a TV or computer screen. However, static electricity has been a serious industrial problem. The age of electronics brought with it new problems associated with static electricity and electrostatic discharge. And, as electronic devices became faster and smaller, their sensitivity to ESD increased. In this work, We are study on the control technique of electo-static discharges using semiconductor circuits. Our circuits are prevented well to electrostatic shock or damages from triboelectric charging in cars everyday life.

• 한국전기전자재료학회논문지
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• 제20권6호
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• pp.496-501
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• 2007

In order to enhance sintering characteristics on the $ZnO-Pr_6O_{11}$ based multilayer chip varistors (MLVs), a response surface analysis using central composite design method were carried out. As a result, varistor voltage($V_{1mA}$), nonlinear coefficient ($\alpha$), leakage current ($I_L$) and capacitance (C) were considered to be mainly affected by sintered temperature and holding time. MLVs sintered at $1200^{\circ}C$ and above $1200^{\circ}C$ revealed poor electrical characteristics, possibly due to the reaction between electrode materials(Pd) and $ZnO-Pr_6O_{11}$ based ceramics. On the sintering temperature range $1150{\sim}1175^{\circ}C$, nonlinear coefficient ($\alpha$) and leakage current ($I_L$) were shown to be $60{\sim}69$ and below $0.3{\mu}A$, respectively. In particular, MLVs sintered at $1175^{\circ}C$, 1.5 hr and $2^{\circ}C/hr$ (cooling speed) showed stable ESD(Electrical Static Discharge) characteristics under the condition of 10 times at 8 Kv with deviation varistor voltage, and deviation nonlinear coefficient were 0.3% and 0.33% (at positive), 0.55% (at negative), respectively.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.256-257
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• 2007

정전기방전(Electro-Static Discharge)에 의한 피해는 전기전자제품의 파괴, 분체의 유도성 폭발, 도장 시 화재 등의 산업 각 분야에 걸쳐 인명이나 물질적 형태로 방대하게 발생하고 있다. 본 논문에서는 이와 같은 여러 형태의 ESD 피해형태 중 전기전자제품 관련분야에 대한 국내외적인 동향을 소개하고자 한다. 반도체, 디스플레이, 등 전기전자 산업분야의 소형화, 고속화는 ESD에 대한 민감도를 증가시키고 있으며, 전기전자 환경의 모든 산업분야에서 제품의 생산성, 신뢰성, 안전성에 커다란 영향을 미치고 있다. 그러므로 ESD 관련 국내 산업의 피해실태와 원인, ESD 방지를 위한 국내기술의 수준을 파악하고, 국제적인 기술동향을 분석하는 것은 매우 중요한 일이다. 이를 바탕으로 한 국내 관련 산업의 국제적인 경쟁력 확보를 위한 국가차원의 관리시스템 및 교육제도 도입성의 필요성을 제시하고자 한다.

• Journal of Power Electronics
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• 제12권6호
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• pp.947-953
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• 2012

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

• 전기전자학회논문지
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• 제13권1호
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• pp.87-93
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• 2009

본 논문에서는 높은 홀딩 전압을 갖는 사이리스터(SCR; Silicon Controlled Rectifier)구조에 기반 한 새로운 구조의 ESD(Electro-Static Discharge) 보호 소자를 제안하였다. 홀딩전압은 애노드단을 감싸고 있는 n-well에 p+ 캐소드를 확장시키고, 캐소드단을 n-well로 추가함으로써 홀딩전압을 증가시킬 수 있다. 제안된 소자는 높은 홀딩전압 특성으로 높은 래치업 면역성을 갖는다. 본 연구에서 제안된 소자의 전기적 특성, 온도특성, ESD 감내특성을 확인하기 위하여 TCAD 시뮬레이션 툴을 이용하여 시뮬레이션을 수행하였다. 시뮬레이션 결과 제안된 소자는 10.5V의 트리거 전압과 3.6V의 홀딩전압을 갖는다. 그리고 추가적인 n-well과 확장된 p+의 사이즈 변화로 4V이상의 홀딩전압을 갖는 것을 확인하였다.