• ETRI Journal
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• v.32 no.1
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• pp.166-168
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• 2010

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.587-590
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• 2000

For high-accuracy signal processing of differential capacitance transducers, an interface circuitry based on a switched-capacitor sample/hold circuit is developed. Driven by nonoverlapping two-phase clocks, the interface produces the output voltage which is proportional to the ratio of difference-to-sum of two capacitors of a differential transducer. Performances of a prototype chip fabricated using 0.6 $\mu\textrm{m}$ n-well CMOS process were measured and compared with those simulated by HSPICE. The measured results indicate that 0.1% resolution is achievable with the proposed interface and the temperature-dependence of the interface is small enough fur practical applications.

• Journal of Advanced Navigation Technology
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• v.28 no.2
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• pp.246-249
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• 2024

In this paper, we present a miniaturized differential line (DL) using inductance-enhanced corrugated ground planes (LCGP) for effective common-mode (CM) noise suppression in high-speed packages and printed circuit boards. The LCGP-DL demonstrates the CM noise suppression in the frequency range from 2.09 GHz to 3.6 GHz. Furthermore, to achieve the same low cutoff frequency, the LCGP-DL accomplishes a remarkable 23.2% reduction in size compared to a reference DL.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.2
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• pp.24-33
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• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.1
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• pp.1-5
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• 2011

The basic signals for electronic engine control are velocity and degree of the engine cam shaft. The CPS sensor used for this signal and magnetic pick-up type CPS sensor is more popular. It is very important thing analyze this signal correctly. If there are some mistakes at the analysis, like a noise, The engine do not working at the best status, it will generate some noise, emit exhaust fumes and waste more gases. In general way to analysis this signal, you use zero-level detector circuit and in order to reduce the error you must use another sensor like a TDC sensor. In this paper, We proposed the analysis method using electronics circuits for magnetic pick-up type CPS sensor. We designed Comparison level detector circuit, Differential circuit and Full-rectifier circuit for detected the Long tooth and Short tooth level correctly without another sensor. We expected it is useful for more reliable engine control.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.286-288
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• 2003

In this paper, in order to obtain a large differential phase shift with a little change in applied voltage, a ferroelectric reflective load circuit has been designed on top of barium strontium titanate $(Ba,Sr)TiO_3$ [BST] thin film. The design of the ferroelectric reflection-type phase shifter is based on a reflection theory of terminating circuit, which has a reflection-type analogue phase shifter with two ports terminated in symmetric phase-controllable reflective networks. To achieve large amounts of phase shift in low bias-voltage range, the effects of change of capacitance and transmission line connected with two coupled ports of a 3-dB $90^{\circ}$ branch-line hybrid coupler have been investigated. A large phase shift with a small capacitance change in the parallel terminating circuit has been demonstrated in the paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.635-637
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• 2000

To analyze the transient state of an induction motor, there have been studies for using the magnetic equivalent circuit method (MECM) instead of the time differential finite-element method, MECM which analyzes magnetic equivalent circuits after converting each part of an electric machine into the magnetic circuit elements. has the merits of short calculation-time and comparatively accurate results. To analyze an electric machine with MECM, we have to replace stator and rotor with the magnetic elements and express the air gap, where electromechanical energy conversion takes place, with the permeance. So in this paper, to analyze an Induction Motor with MECM, we express the magnetic equivalent circuit as algebraic equations and then as the matrix for solving easily them.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.