• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1147-1156
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• 2001

In this paper, a new design architecture of radar signal processor in real time is proposed. It has been designed and implemented under the consideration to minimize the inter-processor communication overhead and to maintain the coherence in Doppler pulse domain and in range domain. Its structure can be easily reconfigured and reprogrammed in accordance with an addition of function algorithm or a modification of operational scenario. As we designed a task configuration for parallel processing from measures of computation time for function algorithms and transmission time for results by signal processing, data exchange between processors for performing of function algorithms could be fully removed. Morocco-2 board equipped ADSP-21060 processor of Analog Devices inc. and APEX-3.2 developed for SHARC DSP were used to construct the radar signal processor.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.342-344
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• 1997

Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.873-874
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• 2006

In this paper, we have developed a ventricular fibrillation detection system based on DSP processor. The developed system was able to detect VF in real time correctly and quickly. We compared the performance of the floating point simulation with that of fixed point simulation. The computational cost of fixed point simulation was remarkably reduced than that of floating point simulation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.443-446
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• 2005

This paper presents the results of the design and implementation of the airborne pulse doppler radar signal processor using high multi-DSP for the multi-function radar capability such as short-range, midium-range, and long-range depending on the mission of the vehicle. Particularly, the radar signal processor is developed using two DSP boards in parallel for the various radar signal processing algorithm. The key algorithms include LFM chirp waveform-based pulse compression, MTI clutter filter, MTD processor, adaptive CFAR, and clutter map. Especially airborne moving clutter Doppler spectrum compensation algorithm such as TACCAR is implemented for the multi-mode airborne radar system. The test results shows the good Doppler spectral separation for the clutter and the moving target in the flight test environment using helicopter

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.4
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• pp.485-492
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• 2006

This paper deals with implementation of network for distributed control system of a humanoid robot ISHURO(Inha Semyung Humanoid Robot). A humanoid robot needs much degree of freedom structurally and much data for having flexible movement. To realize such a humanoid robot, distributed control method is preferred to the centralized one since it gives a compactness, modularity and flexibility for the controllers. For organizing distributed control system of a humanoid robot, a control processor on a board is needed to individually control the joint motor and communication technology between the processors is required to transmit its information within control time. The processor is DSP-based processor and includes CAN network on a chip. It shares the computational load such as monitoring the sensor information and controlling the actuator between each of modules. In this paper, the communication architecture is suggested and its message protocol are discussed including message structure, time consumption for transmission, and controller structure at the view of distributed control for a humanoid robot. All of the sequence are simulated with Matlab and then verified with real walking experiment by ISHURO.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.4
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• pp.362-368
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• 2001

The goal of this paper is development ofa DSP based three phase power quality analyzer. Power analysis algorithm is a correlation function and it is accomplished using stand alone type TMS320C31 DSP(digital signal processor)board. Results of power analysis are displayed by LCD and D/A converter on the proposed system. Finally, this paper also goes on to discuss the performance of an instrument prototype, compared with one of those foreign models, both in terms of accuracy and speed of measurement.