• 한국전기전자재료학회논문지
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• 제31권4호
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• pp.261-266
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• 2018

When the clamp meter approaches the electric path where current is flowing, leakage current can be measured at a distance from the electric current because the induced current increases as the magnitude of the current increases and approaches nearer to the electric path. Therefore, measurements were carried out from a distance to avoid this effect. In addition, the measured values differ depending on the location of the power line that penetrates the ZCT of the clamp meter, thus measurements were performed at a location where this effect was minimized. The fraction of compliant branch circuits, whose leakage current was lower than 1.00 mA, was found to be 69.0% out of the total of 439 branch circuits, while the percentage of compliant branch circuits having an insulation resistance higher than $0.20M{\Omega}$ was found to be 93.2%. The reason why the percentage of compliant branch circuits with low leakage current was low might be due to the inclusion of capacitive leakage current in the total measured leakage current.

• Journal of Power Electronics
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• 제15권2호
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• pp.346-355
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• 2015

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters ($K_p$, $K_i$ and $K_d$) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient $K_d$ is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

• Journal of Power Electronics
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• 제17권3호
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

• 한국전기전자재료학회논문지
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• 제26권7호
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• pp.515-521
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• 2013

Magnetoelectric(ME) bulk composites with PZT-PNN-PZN/$Fe_2O_4$ were prepared by using a conventional ceramic methods and investigated on the ME voltage vs frequency of ac magnetic fields. We made the electric equivalent circuits by using the Maxwell-Wagner model and simulated the frequency dependence of ME voltage in low frequency region. ME devices were described by a series of two equivalent circuits of piezoelectric and magnetic, which have the relaxation time ${\tau}$ due to the interaction between ME device and load resistor. Equivalent circuit of piezoelectric material is independent of frequency. However ferrite magnetic materials have Debye absorption and dipolar dispersion, whose equivalent circuit is a function of frequency. Therefore we suggest the resistance in the equivalent circuit is proportion to $1+{\omega}^2{\tau}^2$ and the capacitance is in inverse proportion to $1+{\omega}^2{\tau}^2$ in the magnetic materials.

• 한국정보통신학회논문지
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• 제11권3호
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• pp.491-499
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• 2007

본 논문에서는 Reed-Muller 전개식에 의한 3치 논리 회로를 설계하는 한 가지 방법을 제시하였다. 제시된 3치 논리 회로의 설계 방법은 Reed-Muller 전개식의 계수에 대하여 모든 변수의 차수를 검사하여 RME 모듈(Reed-Muller Expansions module)의 수를 최소화하는 최적의 제어 입력 변수의 순서를 결정한다. 최적의 제어 입력 변수의 순서는 회로 비용 행렬의 계산에 사용되며, 이 회로 비용 행렬의 계산 결과를 이용하여 Reed-Muller 전개식에 의한 RME 모듈의 나무 구조의 3치 논리 회로를 설계한다. 제시된 방법은 최적 제어 입력 변수를 찾는데 유일하게 단위시간 내에 수행되며, 컴퓨터 프로그램이 가능하고, 프로그래밍 수행 시간이 $3^n$이다.

• 한국군사과학기술학회지
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• 제26권1호
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• pp.64-71
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• 2023

In the recent defence industries, it is required to develop the small and low cost embedded systems for guided missiles. According to the characteristics of guided missiles, the mission is conducted with multiple phases, which include a squib activation phase. By considering the unexpected squib activation, the squib system should be disabled after the launch of a guided missile. Therefore, the squib system needs to include the functions of the safe ignition and status check. This paper presents the squib ignition and status check circuits design for the compact embedded systems in guided missiles. Validation results show that for the functions of the squib ignition and status check, the presented circuits design performs well. The designed circuits also were implemented with various electronic devices and validated by the ground and flight tests.

• 센서학회지
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• 제15권2호
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• 한국산학기술학회논문지
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• 제13권11호
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• pp.5471-5478
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• 2012

본 논문에서는 SURF 알고리즘을 이용하여 PCB에 발생하는 불량 중 한 형태인 쇼트-서킷 불량을 탐지하는 기술을 제안한다. 제안하는 방법의 기본적인 절차는 SURF를 이용하여 샘플 영상과 입력된 영상에서 특징점 추출, 특징점 매칭 및 매칭 결과를 이용한 원근변환 수행, 검사 위치 관심영역 추출, 이진화 및 쇼트-서킷 추출, 결과 검증 순이다. 본 논문에서 제안하는 방식은 수작업으로 진행되는 후 공정의 특징 상, 검사하고자 하는 PCB의 놓여진 위치와 각도가 균일하지 않고 제각각으로 놓여 있는 경우에도 강건하게 쇼트-서킷 불량을 탐지하는 것에 중점을 두고 있다. 이 방법은 PCB가 놓여진 위치와 각도가 다양한 경우에도 불량을 탐지할 수 있음을 보이며, 탐지율 및 탐지시간 관점에서 기존의 수작업으로 검사하는 경우보다 우수함을 실험을 통하여 보인다.

• 한국철도학회논문집
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• 제15권6호
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• pp.604-608
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• 2012

열차의 위치는 전통적으로 궤도회로를 사용하여 검지하였으나 CBTC와 같은 최근의 열차제어 시스템은 지상신호설비를 최소화 하기 위하여 궤도회로를 사용하지 않고 열차를 검지하는 방식을 사용한다. 따라서 궤도회로를 사용하지 않고 열차의 정확한 위치를 검지하는 시스템에 대한 관심이 증대되고 있다. 또한 기존의 궤도회로 사용구간에도 단락감도 저하시 안정적으로 열차검지를 위하여 비접촉식 열차검지장치를 보완 설치한다. 본 논문은 비 접촉식 열차검지기 장치의 일종으로 자기장의 변화에 따른 전류위상차를 이용하여 열차검지시스템을 설계하고 시제품을 제작하여 열차검지 성능과 설계조건 등을 판단하였으며, 기존 궤도회로장치에 비하여 다양한 장점이 있음을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.