JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits

  • Wang, Wei (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Xu, Min (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Liu, Jichao (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Li, Na (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Zhang, Ting (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Jiang, Sitao (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Zhang, Lu (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Wang, Huan (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications) ;
  • Gao, Jian (College of Electronic Science Engineering, Nanjing University of Posts and Telecommunications)
  • Received : 2014.08.19
  • Accepted : 2014.12.27
  • Published : 2015.02.28
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Abstract

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

Keywords

References

  1. R. F. Lu, Y. P. Lu, S. Y. Lee, et al, "Terahertz response in single-walled carbon nanotube transistor: a real-time quantum dynamics simulation", Nanotechnology, Vol. 20, no. 50, pp. 505401, 2009. https://doi.org/10.1088/0957-4484/20/50/505401
  2. D. Kienle, F. Leonard, "Terahertz response of carbon nanotube transistors", Phys. Rev. Lett., Vol. 103, no. 2, pp. 026601, 2000. https://doi.org/10.1103/PhysRevLett.103.026601
  3. S. J. Tans, A. R. M. Verschueren, C. Dekker, "Room-temperature transistor based on a single carbon nanotube", Nature, Vol. 393, no. 7, pp. 49-52, 1998. https://doi.org/10.1038/29954
  4. M. Shulaker, G. Hills, N. Patil, H. Wei, H. Y. Chen, et al, "Carbon nanotube computer", Nature, Vol. 501, pp. 526-530, 2013. https://doi.org/10.1038/nature12502
  5. M. Shulaker, J. V. Rethy, G. Hills, et al, "Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon nanotube FETs", in Proc. Int., pp. 112-113, 2013.
  6. A.Hazeghi, T. Krishnamohan, H.Wong, "Schottky-barrier carbon nanotube field-effect transistor modeling", IEEE Trans. Electron Devices, Vol. 54, no. 3, pp. 439-445, Mar. 2007. https://doi.org/10.1109/TED.2006.890384
  7. J.Guo, M. Lundstrom, S.Datta, "Performance projections for ballistic carbon nanotube field-effect transistors", Appl. Phys. Lett., Vol. 80, no. 17, pp. 3192-3194, Apr. 2002. https://doi.org/10.1063/1.1474604
  8. G. Fiori, G. Iannaccone, G. Klimeck, "A three-dimensional simulation study of the performance of carbon nanotube field-effect transistors with doped reservoirs and realistic geometry", IEEE Trans. Electron Devices, Vol.53, no. 8, pp. 1782-1788, Aug. 2006. https://doi.org/10.1109/TED.2006.878018
  9. A. A. Orouji, Z. Arefinia, "Detailed simulation study of a dual material gate carbon nanotube field-effect transistor", Phys. E: Low-dimensional Syst Nanostructures, Vol. 41, no. 10, pp. 552-557, Feb. 2009. https://doi.org/10.1016/j.physe.2008.10.005
  10. X. H. Liu, H. L. Zhao, T. Y. Li, et al, "Improvement on the electron transport efficiency of the carbon nanotube field effect transistor device by introducing heterogeneous-dual-metal-gate structure", Acta. Phys. Sin., Vol. 62, no. 14, pp. 147308, 2013.
  11. Z. Arefinia, A. A. Orouji, "Quantum simulation study of a new carbon nanotube field-effect transistor with electrically induced source/drain extension", IEEE Trans. Device Mater Reliab., Vol. 9, no. 2, pp. 237-243, Jun. 2009. https://doi.org/10.1109/TDMR.2009.2015458
  12. T. S. Xia, L. F. Register, S. K. Banerjee, "Simulation study of the carbon nanotube field effect transistors beyond the complex band structure effect", Solid-State Electron, Vol. 49, no. 5, pp. 860-864, May. 2005. https://doi.org/10.1016/j.sse.2005.02.002
  13. J. Guo, S. Hasan, A.Javey, et al, "Assessment of high- frequency performance potential for carbon nanotube transistors", IEEE Trans. Nanotechnol., Vol. 4, no. 6, pp. 715-721, Nov. 2005. https://doi.org/10.1109/TNANO.2005.858601
  14. L. Chen, D. L. Pulfrey, "Comparison of p-i-n and n-i-n carbon nanotube FETs regarding high-frequency performance", Solid-State Electron, Vol. 53, no. 9, pp. 935-939, 2009. https://doi.org/10.1016/j.sse.2009.05.006
  15. W. Wang, X. Yang, N. Li, et al, "The high-frequency performance of hetero-material-gate CNTFETs with gate underlap", Fullerenes, Nanotubes and Carbon Nanostructures, 2014.
  16. W. Long, H. Ou, J. Kuo, and K. K. Chin, "Dual-material gate(DMG) field effect transistors" IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 865-870, May 1999. https://doi.org/10.1109/16.760391
  17. I. Polishchuk, P. Ranade, T. J. King, and C. Hu, "Dual work function metal gate CMOS technology using metal interdiffusion", IEEE Electron Device Lett., vol. 22, no. 9, pp. 444-446, Sep. 2001. https://doi.org/10.1109/55.944334
  18. Z. Zhang, S. C. Song, C. Huffman, et al, "Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process", Electrochem. Solid - State Lett., Vol. 8, no. 10, pp. G271-G274, 2005. https://doi.org/10.1149/1.2030447
  19. S. C. Song, Z. B. Zhang, M. M. Hussain, et al, "Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration" , VLSI Symp. Tech. Dig., pp. 13-14, 2006.
  20. Ji Cao, Adrian M. Lonescu, "Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors", Solid-State Electron, Vol. 74, pp.121-125, 2012. https://doi.org/10.1016/j.sse.2012.04.022
  21. Dinh Sy Hien, Nguyen Thi Luong, Thi Tran Anh Tuan, and Dinh Viet Nga, "3D Simulation of coaxial carbon nanotube field effect transistor", Journal of Physics: Conference Series, Vol. 187, no. 1, pp. 012061, 2009.
  22. Orouji A A, Arefinia Z, "Detailed simulation study of a dual material gate carbon nanotube field-effect transistor", Phys E: Low-dimensional Syst. Nanostructures, Vol. 41, no. 4, pp. 552-557, Feb. 2009. https://doi.org/10.1016/j.physe.2008.10.005
  23. Datta S, "Nanoscale device modeling: the Green's function method", Superlatt Microstruct, Vol. 28, no. 4, pp. 253-278, Oct. 2000. https://doi.org/10.1006/spmi.2000.0920
  24. W. Wang, T. Zhang, L. Zhang, et al, "High-frequency and switching performance investigations of novel lightly doped drain and source hetero-material-gate CNTFET", Materials Science in Semiconductor Processing, Vol. 21, pp. 132-139, 2014. https://doi.org/10.1016/j.mssp.2014.01.036
  25. Koswatta S O, Lundstrom M S, Nikonov D E, "Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling", Nano. Lett., Vol. 7, no. 5, pp. 1160-1164, 2007. https://doi.org/10.1021/nl062843f
  26. Koswatta S O, Lundstrom M S, Anantram M P, et al, "Simulation of phonon-assisted band-to-band tunneling in carbon nanotube field-effect transistors", Applied Phy. Lett., Vol. 87, no. 25, pp. 253107, 2005. https://doi.org/10.1063/1.2146065
  27. Arefinia Z., "Investigation of the performance and band-to-band tunneling effect of a new double-halo-doping carbon nanotube field-effect transistor", Phys E: Low-dimensional Syst. Nanostructures, Vol. 41, no. 10, pp. 1767-1771, 2009. https://doi.org/10.1016/j.physe.2009.06.008
  28. J. Appenzeller, Y.-M. Lin, J. Knoch, Ph. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors", Phy. Rev. Lett., Vol. 93, no. 19, pp. 2004.
  29. Hien D. S., Luong N. T., Tuan T. T. A., et al, "3D Simulation of coaxial carbon nanotube field effect transistor", Journal of Physics, Vol. 198, no. 1, pp. 012061, 2009.
  30. R. Yousefi, M. Shabani, M. Arjmandi, and S. S. Ghoreishi, "A computational study on electrical characteristics of a novel band-to-band tunneling graphene nanoribbon FET", Superlattices and Microstructures, Vol. 60, pp. 169-178, Aug. 2013. https://doi.org/10.1016/j.spmi.2013.05.003
  31. A. Naderi, P. Keshavarzi, "Novel carbon nanotube field effect transistor with graded double halo channel", Superlattices and Microstructures, Vol. 51, no. 5, pp. 668-679, May. 2012. https://doi.org/10.1016/j.spmi.2012.02.005
  32. Chris Dwyer, Moky Cheung, and Daniel J. Sorin, "Semi-empirical spice models for Carbon Nanotube FET logic", IEEE Conference on Nanotechnology, pp.386-388, 2004.
  33. Burke PJ, "An RF circuit model for carbon nanotubes", IEEE Trans. Nanotechnol., pp. 393-396, 2002.
  34. Yamacli S, Avci M, "Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation", Mathematical and Computer Modelling, Vol. 58, no. 1, pp. 368-378, 2013. https://doi.org/10.1016/j.mcm.2012.11.014
  35. Rosenblatt S, Yaish Y, Park J, et al, "High performance electrolyte gated carbon nanotube transistors", Nano. Let., Vol. 2, no. 8, pp. 869-872, 2002. https://doi.org/10.1021/nl025639a
  36. Guo J, Goasguen S, Lundstrom M, et al, "Metal-insulator-semiconductor electrostatics of carbon nanotubes", Applied Physics Letters, Vol. 81, no. 8, pp. 1486-1488, 2002. https://doi.org/10.1063/1.1502188
  37. Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection", IEEE Trans. Nanotechnol, Vol. 9, no. 1, pp. 30-37, Jan. 2010. https://doi.org/10.1109/TNANO.2009.2025128
  38. International Technology Roadmap for Semiconductors, available at http://public.itrs.net.