• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.27-31
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• 2003

RF characteristics of CPW(coplanar waveguide) pattern with bonding pads used in flip-chip packaging of GaAs is studied in the frequency range of 1 GHz to 35 GHz. Simulation, fabrication and evaluation are performed for the proposed patterns. Measurement results show proposed patterns have similar properties of $S_{11}$below -31 dB and $S_{21}$ above -0.19 dB with typical CPW In addition RF properties are improved with the increase of width of ground line. This indicates CPW structure with bonding pads keeps RF characteristics of typical CPW.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.09a
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• pp.55-85
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• 2000

MEMS(Micro Electro Mechanical System) technology. MEMS Inertial Sensors promise a new wide market for many areas -Challenge. significant cost reduction by wafer level packaging and testing. decreasing of power consumption by miniaturization. enhancing of performance and reliability. on-chip integration for multiplicity. MEMS is newly emerging technology.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.711-712
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• 2009

MCP 기술을 이용한 반도체 칩에서 문제가 되는 방열문제를 해결하기 위한 방법으로 열전 냉각 소자를 이용하여 열을 방출 시키는 방법에 관하여 연구를 수행하였다. 시뮬레이션을 통하여 열전 소자가 작동할 때, 흡수하는 열량을 계산할 수 있었으며, 열전 소자의 냉각 성능도 평가 할 수 있었다. 이러한 열 해석 및 열전 해석을 통하여 적층 구조의 MCP 모듈을 위한 열 설계 및 효율적 냉각을 가능하게 할 수 있을 것이다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.203-207
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• 2002

CSP(Chip Size Packaging) SAW Filter Package에 대해서, 유한요소해석(Finite Element Analysis) 컴퓨터 Simulation 프로그램인 ANSYS를 이용하여 Package의 온도 분포를 해석하였다. 신뢰성(reliability) Test 조건에서 Transient Thermal Simulation을 한 후, 조건을 변화시켜 가면서 Chip 내부 온도가 어떻게 변화하는지 알아보았다. Chip에 1.8 hour 동안 4W의 열원을 주고, 주위는 2$0^{\circ}C$ 자연대류로 놓고 Transient Thermal Simulation한 결과는 약 99$^{\circ}C$로, 허용 가능한 온도인 11$0^{\circ}C$보다 약 11$^{\circ}C$ 낮음을 알 수 있었다. 또한 이는 실험값인 약 95$^{\circ}C$와 유사한 값을 나타내었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• Journal of the Korean Society of Industry Convergence
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• v.12 no.4
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• pp.215-219
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• 2009

A packaging technology based on flip-chip bonding and Pb-free solder for silicon pressure sensors on printed circuit board (PCB) is presented. First, the bump formation process was conducted by Pb-free solder. Ag-Sn-Cu solder and the pressed-screen printing method were used to fabricate solder bumps. The fabricated solder bumps had $189-223{\mu}m$ width, $120-160{\mu}m$ thickness, and 5.4-6.9 standard deviation. Also, shear tests was conducted to measure the bump shear strength by a Dage 2400 PC shear tester; the average shear strength was 74 g at 0.125 mm/s of test speed and $5{\mu}m$ shear height. Then, silicon pressure sensor packaging was implemented using the Pb-free solder and bump formation process. The characteristics of the pressure sensor were analogous to the results obtained when the pressure sensor dice are assembled and packaged using the standard wire-bonding technique.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.145-164
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• 2004

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.47-66
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• 2006