• 한국레이저가공학회:학술대회논문집
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• 한국레이저가공학회 2006년도 추계학술발표대회 논문집
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• pp.53-81
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• 2006

A COG(Chip on Glass) bonding process that is one of display packaging technology and bonds between driver IC chip and a glass panel using ACF(Anisotropic Conductive Film)has been investigated by using diode laser. This method is possible to raise cure temperature of ACF within one second and can reduce the total process time for COG bonding by a conventional method such as a hot plate. Also we can get good pressure mark on the surface of electrodes and higher bonding strength than that by convention method. Results show that laser COG bonding can give low pressure bonding and decrease a warpage of panel. We believe that it can be applied to fine pitch module.

• Journal of Welding and Joining
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• 제22권3호
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• pp.62-68
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• 2004

The strip Au bumps are bonded using longitudinal ultrasonic far the electronic package. Au bumps on the chip and substrate are aligned in a crossed shape, and the ultrasonic is imposed on the chip to form the solid-state bond between the Au bumps. Deformed bump shapes are calculated using the finite element method, and the bond strength is measured experimentally. The crossed strip Au bumps are deformed similar to the saddle, which provides larger contact surface area and higher friction force. Compared with the previous bonding method between the Au bump and planar pad, higher bond strength is obtained using the crossed strip bumps.

• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 마이크로전자및패키징학회지
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• 제14권4호
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• pp.79-85
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• 2007

본 연구의 목적은 OSP, 전해 Au과 무전해 Ni/Au로써 표면처리를 달리한 연성회로기판 상에 Au 스터드 플립칩 범프의 초음파 접합 가능성을 연구하는 것이었다. Au 스터드 범프는 표면처리 방법에 상관없이 성공적으로 연성회로기판의 패드 상에 초음파 접합되었다 접합 강도는 접합 시간에 민감하게 영향을 받았다. 접합 시간이 길어짐에 따라 접합 강도는 증가하였으나, 2초 이상의 접합 시간에서는 이웃 범프끼리 단락되는 bridge 현상이 발생하였다. 최적 접합조건은 OSP 처리된 가판상에 0.5초간 초음파 접합하는 것이었다.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.91-96
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• 2014

TSV기술은 실리콘 칩에 관통 홀(through silicon via)을 형성하고, 비아 내부에 전도성 금속으로 채워 수직으로 쌓아 올려 칩의 집적도를 향상시키는 3차원 패키징 기술로서, 와이어 본딩(wire bonding)방식으로 접속하는 기존의 방식에 비해 배선의 거리를 크게 단축시킬 수 있다. 이를 통해 빠른 처리 속도, 낮은 소비전력, 높은 소자밀도를 얻을 수 있다. 본 연구에서는 웨이퍼 레벨에서의 TSV 충전 경향을 조사하기 위하여, 실리콘의 칩 레벨에서부터 4" 웨이퍼까지 전해 도금법을 이용하여 Cu를 충전하였다. Cu 충전을 위한 도금액은 CuSO4 5H2O, H2SO4 와 소량의 첨가제로 구성하였다. 양극은 Pt를 사용하였으며, 음극은 $0.5{\times}0.5 cm^2{\sim}5{\times}5cm^2$ 실리콘 칩과 4" 실리콘 wafer를 사용하였다. 실험 결과, $0.5{\times}0.5cm^2$ 실리콘 칩을 이용하여 양극과 음극과의 거리에 따라 충전률을 비교하여 전극간 거리가 4 cm일 때 충전률이 가장 양호하였다. $5{\times}5cm^2$ 실리콘 칩의 경우, 전류 공급위치로부터 0~0.5 cm 거리에 위치한 TSV의 경우 100%의 Cu충전률을 보였고, 4.5~5 cm 거리에 위치한 TSV의 경우 충전률이 약 95%로 비아의 입구 부분이 완전히 충전되지 않는 경향을 보였다. 전극에서 멀리 떨어져있는 TSV에서 Cu 충전률이 감소하였으며, 안정된 충전을 위하여 전류를 인가하는 시간을 2 hrs에서 2.5 hrs로 증가시켜 4" 웨이퍼에서 양호한 TSV 충전을 할 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.111-114
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• 2001

Optical transmitter and receiver are the essential components for optical communication. For these components, butterfly type packages are used which are comprised of metal housing, multilayer ceramic inserts, lead and window. In this study, 2.5 Gbps DFB(Distributed -Feedback) LD(Laser Diode) package was fabricated and characterized. Metal housing showed good thermal conductivity (200W/mK) and well matched TCE(6.7ppm/K) with GaAs chip. Ceramic inserts also showed good VSWR(Voltage Standing Wave Ratio) characteristics(<2.0). By brazing technology, all the elements were combined and sealed. RF characteristics of the package mounted on the PWB was also tested.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.203-215
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• 2002

Using eutectic In-Ag and Bi-Sn solder materials, we developed the COG technique having a minimum pitch of 50 ${\mu}{\textrm}{m}$. The maximum temperature in this process is $160^{\circ}C$. We fabricated spherical and uniform solder bumps by controlling the microstructure of Bi-Sn solder bumps. The contact resistances of Bi-Sn solder joints were 19 m$\Omega$ at $80{\mu}{\textrm}{m}$ pitch and 60 m$\Omega$ at $80{\mu}{\textrm}{m}$ pitch, respectively. These values are much lower than the contact resistance of the conventional ACF bonding. The contact resistances of the solder joint are almost the same before and after the underfill process. The contact resistance of the underfilled Bi-Sn solder joint did not change even after reliability test.

• 한국정밀공학회지
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• 제32권9호
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• pp.799-805
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• 2015

The further development of information, communication and digital media technologies requires the use of advanced, miniaturized semiconductor chips that operate at a high frequency. Die bonding and wire bonding methods for semiconductor packaging have been replaced by direct attachment to the substrate after forming a bump on the chip. However, the height of the bump or ball is an important factor for defects during assembly. This paper proposes an algorithm to measure the height of the bumps or balls in semiconductor packaging with greater accuracy. The performance of the proposed algorithm is experimentally validated. Non-contact 3D measurements of a shiny round ball is quite difficult, and it is not easy to obtain accurate data. This paper thus proposes an optical method and technique to improve the measurement accuracy.