Korean Journal of Metals and Materials (대한금속재료학회지)

The Korean Institute of Metals and Materials (대한금속재료학회)
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Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages

칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정

  • Kim, Min-Young (Materials Science and Engineering, Hongik University) ;
  • Oh, Taek-Soo (Materials Science and Engineering, Hongik University) ;
  • Oh, Tae-Sung (Materials Science and Engineering, Hongik University)
  • 김민영 (홍익대학교 신소재공학과) ;
  • 오택수 (홍익대학교 신소재공학과) ;
  • 오태성 (홍익대학교 신소재공학과)
  • Received : 2009.10.26
  • Published : 2010.06.22
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Abstract

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

Keywords

Acknowledgement

Supported by : 전자패키지재료연구센터

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