DOI QR코드

DOI QR Code

Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages

칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정

  • Kim, Min-Young (Materials Science and Engineering, Hongik University) ;
  • Oh, Taek-Soo (Materials Science and Engineering, Hongik University) ;
  • Oh, Tae-Sung (Materials Science and Engineering, Hongik University)
  • 김민영 (홍익대학교 신소재공학과) ;
  • 오택수 (홍익대학교 신소재공학과) ;
  • 오태성 (홍익대학교 신소재공학과)
  • Received : 2009.10.26
  • Published : 2010.06.22

Abstract

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

Keywords

Acknowledgement

Supported by : 전자패키지재료연구센터

References

  1. Y. N. Kim, J. M. Koo, S. K. Park, and S. B. Jung, J. Kor. Inst. Met. & Mater. 46, 33 (2008).
  2. J. H. Lee, G. T. Lim, S. T. Yang, M. S. Suh, Q. H. Chung, K. Y. Byun, and Y. B. Park, J. Kor. Inst. Met. & Mater. 46, 310 (2008).
  3. S. K. Lim, J. W. Choi, Y. H. Kim, and T. S. Oh, J. Kor. Inst. Met. & Mater. 46, 585 (2008).
  4. C. M. Oh, N. C. Park, C. W. Han, M. S. Bang, and W. S. Hong, J. Kor. Inst. Met. & Mater. 47, 500 (2009).
  5. P. Arunasalam, H. D. Ackler, and B. G. Sammakia, J. Vac. Sci. Technol. B 24, 1780 (2006) https://doi.org/10.1116/1.2210003
  6. C. Ryu, J. Park, J. S. Pak, K. Y. Lee, T. S. Oh, and J. Kim, IEEE Microwave Wireless Comp. Lett. 17, 855 (2007). https://doi.org/10.1109/LMWC.2007.910485
  7. K. W. Lee, Teck-Soo Oh, J. H. Lee, and T. S. Oh, J. Electron. Mater. 36, 123 (2007). https://doi.org/10.1007/s11664-006-0020-5
  8. W. P. Dow and C. W. Liu, J. Electrochem. Soc. 153, C190 (2006). https://doi.org/10.1149/1.2165743
  9. M. Karnezos, F. Carson, and R. Pendse, "3D Packaging Promises Performance, Reliability Gains with Small Footprints and Lower Profiles", Chip Scale Review, (February 2005).
  10. S. F. Al-Sarawi, D. Abbott, and P. D. Franzon, IEEE Trans. Comp. Packag. Manufact. Technol. B 21, 2 (1988).
  11. R. E. Terrill, Proc. Int. Conf. Multichip Modules, Denver, USA, p.7 (April 1995).
  12. T. Kobayashi, J. Kawasaki, K. Mihara, and H. Honma, Electrochimica Acta 47, 85 (2001). https://doi.org/10.1016/S0013-4686(01)00592-8
  13. D. Varadarajan, C. Y. Lee, A. Krishnamoorthy, D. J. Duquette, and W. N. Gill, J. Electrochem. Soc. 147, 3382 (2000). https://doi.org/10.1149/1.1393910
  14. M. Umemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai, and K. Takahashi, Proc. Electron. Comp. Technol. Conf. Las Vegas, USA, p.616 (June 2004).
  15. J. T. Huang, P. S. Chao, H. J. Hsu, and S. H. Shih, Mater. Sci. Semicon. Process 10, 133 (2007). https://doi.org/10.1016/j.mssp.2007.07.001
  16. Y. Kripesh, S. W. Yoon, V. P. Ganesh, N. Khan, M. D. Rotaru, W. Feng, and M. K. Iyer, IEEE Trans. Adv. Packag. 28, 337 (2005).
  17. H. J. Lee and J. Yu, J. Microelectron. Packag. Soc. 11, 1 (2004).
  18. H. K. Kim and K. N. Tu, Appl. Phys. Lett. 67, 2002 (1995). https://doi.org/10.1063/1.114767
  19. Sn-Ti Binary Systems in "Binary Systems. Part 4: Binary Systems from Mn-Mo to Y-Zr Phase Diagrams, Phase Transition Data, Integral and Partial Quantities of Alloys", Springer Berlin Heidelberg, Berlin (2006).
  20. P. G. Kim, J. W. Jang, T. Y. Lee, and K. N. Tu, J. Appl. Phys. 86, 6746 (1999). https://doi.org/10.1063/1.371751
  21. T. S. Oh, K. Y. Lee, and H. J. Won, IEEE Trans. Comp. Packag. Technol. 32, 909 (2009). https://doi.org/10.1109/TCAPT.2009.2015594
  22. P. Sricharoenchaikit, Proc. Int. Conf. Compound Semicondctor Mfg. Scottdale, USA, p.8 (March 2003).
  23. D. Manessis, R. Patzelt, A. Ostmann, R. Aschenbrenner, H. Reichl, J. Wiese, and C. Modes, IMAPS, Long Beach, USA (Nov. 2004): www.cmst.be/.../17_2004_IMAPS_Long%20Beach_Manessis_paper.pdf
  24. S. W. Yoon, V. Kripesh, A. Viswanath, H. Y. Li, and M. K. Iyer, 55th Electron. Comp. Technol. Conf. Lake Buena Vista, USA, p.100, May-June (2005).
  25. M. Osborne, J. Ling, C. Huynh, I. Qin, and V. McTaggart, IMAPS Device Packag. Conf. Scottdale, USA (March 2005): www.kns.com/UPLOADFILES/DGALLERY/6001.PDF
  26. C. Wang and A. S. Holmes, IEEE Trans. Electron. Packag. Manuf. 24, 109 (2001).