• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.165-180
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• 2004

Phosphor contents are critical to the interfacial reaction and IMC behavior. - If content is too low, the dissolution rate will be very fast. - If content is too much, the cracks during interfacial reaction and the IMCs spalling will easily occur. The spalling of IMCs caused the brittle fracture of solder joint under shear test. IMCs from chemical reaction influences to the mechanical properties and life time. Composition changes from chemical reaction influence to the life time.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.79-92
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• 2004

RoHS compliant products are now being mass-produced. Eco-product(Pb-free+RoHS compliant+Halogen-free) will be possible from 2005. Pb-free flip chip will be qualified by 2004. 4Q. Lead Finish: SnBi-Under mass production Pd PPF-Under small production Matte Sn-will be internally qualified by 2004. 4Q Development of Pb-free Solder Ball: Stable Supply, Cost Down.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.49-54
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• 2001

This paper presents several UBM (Under Bump Metallurgy) systems which are currently used for wafer level solder bumping technology. The advantages and disadvantages of each UBM are summarized from the point of view of process compatability and interface morphological stability.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.183-199
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• 2002

Reliability.The reliability strongly depended on the CTE of underfill resin..The fractured portion was identical with the maximum plastic equivalent strain..1 % or less value of the maximum plastic equivalent strain certified more than 1000 cycle of TCT life. UFB.Bonding accuracy was confirmed within2$2{\mu}{\textrm}{m}$..The fundamental bondability of UFB was confirmed with no damage around aluminum pads. Some dislocations and vacancies were observed at the interface, however, the atomic level bonding was confirmed. CBB.Dry process was applied to UBM removal.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.861-864
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• 1997

Singulation is a process that cutting for separating a chip individually after finishing packaging process(micro BGA etc.). For shortening the process of singulation, we proposed the singulation using multi-blade. This paper introduced a method of multi-blade singulation and investigated a result of application and problems. The efficiency of singulation process was improved five times better than the single-blade by the singulation using Multi-blade.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.51-69
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• 2001

Japan Jisso Technology Roadmap 2001 (JJTR2001) was published by JEITA in April 2001. Future electronic products request further higher assembly technology (ex. Finer pitch packages & components, 3D assembly, etc.) to reduce size and improve performance of the electric products. For LSI Packages, finer ball pitch technology and finer chip connection technology will be developed. For electric components, further size reduction will be developed. For Jisso (assembly) machine, finer pitch assembly and short tact time technology will be developed. Mr. Utsunomiya will present PCB roadmap next.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.45-52
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• 2011

It is known that test methods to evaluate solder joint reliability are die shock test, die shear test, 3points bending test, and thermal shock test. The present study investigated the effects of failure mode on 3 types (as-reflowed, $85^{\circ}C$/85%RH treatment, and $150^{\circ}C$/10hr aging) of solder joints for flip-chip BGA package by using various test methods. The test methods and configurations are reported in detail, i.e. die shock, die shear, 3points bending, and thermal shock test. We focus on the failure mode of solder joints under various tests. The test results indicate that die shock and die shear test method can reveal brittle fracture in flip-chip ball grid array (FCBGA) packages with higher sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.59-65
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• 2011

According to the trends of electronic package to be smaller, thinner and more integrative, Flip Chip Ball Grid Array (FCBGA) become more used for mobile phone. However, the flip chip necessarily generate the heat by the electrical resistance and generated heat is increased due to reduced distribution area of the heat in accordance with the miniaturization trend of the package. Thermal issues can result in problems of devices that are sensitive to temperature and stress. Then the heat can generate problems to the system. In this paper, in order to improve the thermal issues of FCBGA, thermal characteristics of FCBGA was analyzed qualitatively by using the general heat transfer module of Comsol 3.5a and In order to solve thermal issues, flip chip with new micro structure is proposed by the simulation. and also by comparing existing model and analyzing variables such as pitch, height of the pattern and shape of the heat spreader, the improvement of heat dissipation characteristics about 18% was confirmed.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.