• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.2
• /
• pp.88-92
• /
• 2006

We present a microfluidic system with microvalves and a micropump that are easily integrated on the same substrate using the same fabrication process. The fabricated microfluidic system is suitable for use as a disposable device and its characteristics are optimized for use as a micro chemical analysis system (micro-TAS) and lab-on-a-chip. The system is realized by means of a polydimethylsiloxane (PDMS)-glass chip and an indium tin oxide (ITO) heater. We demonstrate the integration of the micropump and microvalves using a new thermopneumatic-actuated PDMS-based microfluidic system. A maximum pumping rate of about 730 nl/min is observed at. a duty ratio of 1 $\%$ and a frequency of 2 Hz with a fixed power of 500 mW. The measured power at flow cut-off is 500 mW for the microvalve whose channel width, depth and membrane thickness were 400 $\mu$m, 110 $\mu$m, and 320 $\mu$m, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.8
• /
• pp.9-16
• /
• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.2
• /
• pp.1364-1369
• /
• 2015

As the wire bonding process has been converted into BUMP process due to the high density integration of semiconductor chip, the telecommunication line connecting to semiconductor chip and external devices have become finer. As a result, a more precise work is necessary. However, it is difficult to control quantity given the nature of high viscosity of PSPI and the yield rate continues to decline due to the inflow of bubble. Therefore, this paper developed the D&P(degassing and pumping) system to remove and supply gas that is generated from coating the high viscosity photosensitive polyimide(PSPI) in the semiconductor BUMP process.

• Journal of the Korean institute of surface engineering
• /
• v.54 no.5
• /
• pp.207-212
• /
• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• Nuclear Engineering and Technology
• /
• v.53 no.4
• /
• pp.1167-1175
• /
• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.09a
• /
• pp.219-225
• /
• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• Journal of Astronomy and Space Sciences
• /
• v.29 no.3
• /
• pp.315-320
• /
• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.4
• /
• pp.87-92
• /
• 2007

A $CaAl_{12}O_{19}:Mn^{4+}$ red phosphor showed the highest emission intensity at a concentration of 0.02mole $Mn^{4+}$ and the high crystallinity and luminescent properties were obtained at $1600^{\circ}C$ firing temperature for 3hr. The synthesized phosphor showed a broad emission band at 658nm wavelength. Red light-emitting diodes(LEDs) were fabricated through the integration of on InGaN UV bare chip and a 1:3 ratio of $CaAl_{12}O_{19}:Mn^{4+}$ and epoxy resin in a single package. This coated LED can be applicable to make White LEDs under excitation energy of UV LED.

• Corrosion Science and Technology
• /
• v.6 no.6
• /
• pp.282-285
• /
• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature / humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the electrochemical migration. Many kinds of metal (Cu, Ag, SnPb, Sn etc) using in electronic packages are failed by ECM. Eutectic SnPb which is used in various electronic packaging structures, that is, printed circuit boards, plastic-encapsulated packages, organic display panels, and tape chip carriers, chip-on-films etc. And the material for soldering (eutectic SnPb) using in electronic package easily makes insulation failure by ECM. In real PCB system, not only metals but also many chemical species are included. And these chemical species act as resources of contamination. Model test systems were developed to characterize the migration phenomena without contamination effect. The serpentine-shape pattern was developed for analyzing relationship of applied voltage bias and failure lifetime by the temperature / humidity biased(THB) test.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.48-55
• /
• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.