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FE-SEM Image Analysis of Junction Interface of Cu Direct Bonding for Semiconductor 3D Chip Stacking

  • 투고 : 2021.09.15
  • 심사 : 2021.10.28
  • 발행 : 2021.10.31

초록

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm2 and 3087 N/cm2. At 2303 N/cm2, the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm2, the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm2 and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

키워드

참고문헌

  1. P. Arunasalam, H. D. Ackler, B. G. Sammakia, Micro-fabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks, J. Vac. Sci. Technol., B24 (2006) 1780.
  2. C. Ryu, J. Park, J. S. Pak, K. Y. Lee, T. S. Oh, J. Kim, Suppression of power/ground inductive impedance and simultaneous switching noise using silicon through-via in a 3D stacked chip package, IEEE Microwave Wireless Comp. Lett., 17 (2007) 855. https://doi.org/10.1109/LMWC.2007.910485
  3. G. Giao, T. Workman, L. Mirkarimi, G. Fountain, J. Theil, G. Guevara, C. Uzoh, B. Lee, P. Liu, P. Mrozek, Chip wafer hybrid bonding with Cu interconnect: high volume manufacturing process compatibility study, Proceeding of the international wafer-level packaging conference (2019).
  4. S. E. Kim, S. Kim, Wafer level Cu-Cu directing bonding for 3D integration, Micro. Eng. 1 (2015) 1-6. https://doi.org/10.1016/0167-9317(83)90008-4
  5. D. R. Frear, S. N. Burchett, H. S. Morgan, J. H. Lau, The mechanics of solder alloy interconnects, Van Nostrand Rein-hold, New york, (1994).
  6. K. S. Kim, H. J. Lee, H. Y. Kim, J. H. Kim, S. Hyun, H. J. Lee, Characterization of interfacial adhesion of Cu-Cu bonding fabricated by thermo-compression bonding process, Transactions of the KSME A, (2010) 929~933.
  7. S. G. Kang, J. Lee, E. S. Kim, N. Lim, S Kim, S. Kim, S. E. Kim, Fabrication and challenges of Cu-to-Cu wafer bonding, Journal of the microelectronics & packaging society, 19(2}, (2012) 29-33. https://doi.org/10.6117/KMEPS.2012.19.2.029
  8. J. W. Kim, M. H. Jeong, E. Carmak, B. Kim, T. Matthias, H. J. Lee, S. Hyun, Y. B. Park, Cu thickness effects on bonding characteristics in Cu-Cu direct bonds, Journal of the microelectronics & packaging society, 17(4), (2010) 61-66.
  9. B. S. Lee, J. H. Back, J. W. Yoon, Effect of sintering conditions on microstructure and mechanical strength of Cu micro-particle sintered joints for high-power semiconductor module applications, Journal of Welding and Joining 37(2), (2019) 26-34. https://doi.org/10.5781/jwj.2019.37.2.5
  10. I. Radu, D. Landru, G. Gaudin, G. Riou, C. Tempesta, F. Letertre, M. Sadaka, Recent developments of Cu-Cu non-thermo compression bonding for wafer to wafer 3D stacking, Ieee International 3D Systems Integration Conference (3DIC) (2010) 1-6.
  11. Y. S. Tang, Y. J. Chang, K. N. Chen, Wafer level Cu-Cu bonding thchnology, Microelectronics Reliability, 52(2) (2012) 312-320. https://doi.org/10.1016/j.microrel.2011.04.016
  12. A. K. Panigrahi, K. N. Chen, Low temperature Cu-Cu bonding technology in 3D integration: an extensive review, Journal of Electronic packaging, 140 (2017) 1.
  13. A. Agrawal, N. Pham, R. Cotrin, A. Andrei, W. Ruythrooren, F. Iker, P. Soussan, Diamond bit cutting for processing high topography wafers, Electronic packaging technology conference, Singapore, (2009).