Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Development of Simple Reconfigurable Access Mechanism for SoC Testing

재구성 가능한 시스템 칩 테스트 제어기술의 개발

  • 김태식 (한양대학교 컴퓨터공학부) ;
  • 민병우 (한양대학교 컴퓨터공학) ;
  • 박성주 (한양대학교 컴퓨터공학부)
  • Published : 2004.08.01
Download PDF
⟨ Previous Next ⟩

Abstract

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

여러 개의 IP 코아로 구성된 SoC(System-on-a-Chip)를 위해, 테스트 래퍼와 스캔 체인의 다양한 연결구성이 가능한 테스트 기술이 제안되고 있다. 본 논문에서는, 테스트 래퍼와 스캔 체인을 효과적으로 재구성하며 테스트 할 수 있는 새로운 SoC 테스트 접근 기법을 소개한다. IEEE 1149.1 및 P1500 기반의 테스트 래퍼를 위해 테스트 래퍼 제어기인 WCLM(Wrapped Core Linking Module)과, WCLM과 맞물려 코아 내부의 스캔 체인에 효과적으로 접근 가능한 TAM(Test Access Mechnism) 구조를 제안한다.

Keywords

References

  1. Y. Zorian, 'Guest editor's introduction: what is infrastructure IP,' Design & Test of Computers, IEEE, Volume: 19, Issue: 3, Pages 3-5, May/Jun 2002 https://doi.org/10.1109/MDT.2002.1003776
  2. Y. Zorian, E. J. Marinissen and S. Dey, 'Testing Embedded-core-based System Chips,' In Proceedings IEEE International Test Conference, pages 130-143, 1998
  3. Erik Jan Marinissen, Hans Dingemanse, Robert Arendsen, Maurice Lousberg, Gerard Bos and Clemens Wouters, 'A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, In Proceedings IEEE International Test Conference, pages 284-293, 1998 https://doi.org/10.1109/TEST.1998.743166
  4. V. Iyengar, K. Chakrabarty and E. J. Marinissen, 'Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip,' In Proceedings IEEE International Test Conference, pages 1023-1032, 2001 https://doi.org/10.1023/A:1014916913577
  5. M. Benabdenebi, W. Maroufi and M. Marzouki, 'Testing TAPed cores and wrapped cores with the same test access mechanism,' Design, Automation and Test in Europe Conference, Proceedings, pages 150-155, 2001 https://doi.org/10.1109/DATE.2001.915016
  6. IEEE Std. 1149.1a-1993
  7. IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/
  8. Lee Whetsel, 'An IEEE 1149.1 Based Test Access Architecture For ICs With Embedded Cores,' In Proceedings IEEE International Test Conference, pages 69-78, 1997 https://doi.org/10.1109/TEST.1997.639596
  9. Steven F. Oakland, 'Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits,' In Proceedings IEEE International Test Conference, pages 628-637, 2000 https://doi.org/10.1109/TEST.2000.894257
  10. Whetsel, L., 'Addressable test ports an approach to testing embedded cores,' In Proceedings IEEE International Test Conference, pages 1055-1064, 1999 https://doi.org/10.1109/TEST.1999.805839
  11. Debashis Bhattacharya, 'Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit,' VLSI Test Symposium, Proceedings. 16th IEEE, pages 8-14, 1998 https://doi.org/10.1109/VTEST.1998.670842
  12. Debashis Bhattacharya, 'Instruction-Driven Wake-up Mechanisms for Snoopy TAP Controller,' VLSI Test Symposium, Proceedings, 17th IEEE, pages 467-472, 1999 https://doi.org/10.1109/VTEST.1999.766705
  13. S. Harrison, G. Noeninckx, P. Horwood and P. Collins, 'Hierachical Boundary-Scan A Scan Chip-Set Solution,' In Proceedings IEEE International Test Conference, pages 480-486, 2001 https://doi.org/10.1109/TEST.2001.966665
  14. B. I. Dervisoglu, 'A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers,' Design Automation Conference, pages 53-58, 2001 https://doi.org/10.1145/378239.378280
  15. M. Benabdenebi, W. Maroufi, andM. Marzouki, 'CAS-BUS: a scalable and reconfigurable test access mechanism for systems on a chip,' Design, Automation and Test inEurpe Conference, Proceedings, pages 141-145, 2000 https://doi.org/10.1109/DATE.2000.840030
  16. E. J. Marinissen, V. Iyengar, and K. Chakrabarty, 'A set of benchmarks for modular testing of SOCs,' In Proceedings IEEE International Test Conference, pages 519-528, 2002