• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.5
• /
• pp.50-56
• /
• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.5
• /
• pp.753-756
• /
• 2012

In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn't use PTAT current. The proposed structure is more simple than the existing structure and doesn't use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12$ppm/^{\circ}C$ from $0^{\circ}C$ to $100^{\circ}C$.

• Current Optics and Photonics
• /
• v.7 no.2
• /
• pp.200-206
• /
• 2023

Near-infrared (NIR) sensing technology using CMOS image sensors is used in many applications, including automobiles, biological inspection, surveillance, and mobile devices. An intuitive way to improve NIR sensitivity is to thicken the light absorption layer (silicon). However, thickened silicon lacks NIR sensitivity and has other disadvantages, such as diminished optical performance (e.g. crosstalk) and difficulty in processing. In this paper, a pixel structure for NIR sensing using a stacked CMOS image sensor is introduced. There are two photodetection layers, a conventional layer and a bottom photodiode, in the stacked CMOS image sensor. The bottom photodiode is used as the NIR absorption layer. Therefore, the suggested pixel structure does not change the thickness of the conventional photodiode. To verify the suggested pixel structure, sensitivity was simulated using an optical simulator. As a result, the sensitivity was improved by a maximum of 130% and 160% at wavelengths of 850 nm and 940 nm, respectively, with a pixel size of 1.2 ㎛. Therefore, the proposed pixel structure is useful for NIR sensing without thickening the silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04b
• /
• pp.180-183
• /
• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• Journal of Sensor Science and Technology
• /
• v.24 no.2
• /
• pp.131-136
• /
• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.465-471
• /
• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.8
• /
• pp.966-974
• /
• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.12
• /
• pp.1-6
• /
• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.

• Journal of the Korean Society of Industry Convergence
• /
• v.5 no.1
• /
• pp.39-43
• /
• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.205-210
• /
• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.