• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.6
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• pp.553-558
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• 2016

A DC-DC converter for CMOS image sensors in bio-sensor chips is proposed. The DC-DC converter generates a PCP voltage, that is an on voltage of a pixel, and an NCP voltage, that is an off voltage of a pixel. The PCP voltage with a ripple voltage of within 1.33V is obtained from a positive charge pump of VPP (=5V) with a ripple voltage of 45.35 by using a regulator. Also, the NCP voltage with a ripple voltage of 0.05mV is obtained from a negative charge pump of VNN (=-2V) with a ripple voltage of 62.8 by using a regulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.924-927
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• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• Journal of IKEEE
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• v.24 no.4
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• pp.975-981
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• 2020

A 10 GHz LC voltage-controlled oscillator (VCO), which controls an amplitude of output signal, is proposed to improve the phase noise. The proposed amplitude control circuit for the LC VCO consists of a peak detector, an amplifier, and a current source. The peak detector is performed detecting the lowest voltage of the output signal by using two diode-connected NMOSFET and a capacitor. The proposed 10 GHz LC VCO with an amplitude control circuit for output signal is designed using a 55 nm CMOS process with a supply voltage of 1.2 V. Its area is 0.0785 ㎟. The amplitude control circuit used in the proposed LC VCO reduces the amplitude variation 242 mV generated in the output signal of the conventional LC VCO to 47 mV. Furthermore, it improves the peak-to-peak time jitter from 8.71 ps to 931 fs.