• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.205-212
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• 2003

In this paper, we propose a simple and efficient hardware-supported antialiasing algorithm and its rendering scheme. The proposed method can efficiently reduce the required memory bandwidth as well as memory size compared to a conventional supersampling when rendering 3D models. In addition, it can provide almost the same high quality scenes as supersampling does. In this paper, we have introduced the RUF (Recently Used Fragment) buffer that stores some or whole parts of a fragment or two more the merged results of fragments that recently used in color calculation. We have also proposed a color calculation algorithm to deteriorate the image quality as referencing the RUF buffer. Because of the efficiency presented in the proposed algorithm, the more number of sampling points increases the more memory saving ratio we can gain relative to the conventional supersampling. In our simulation, the proposed method can reduce the amount of memory size by 31% and the memory bandwidth by 11% with a moderate pixel color difference of 1.3% compared to supersampling for 8 sparse sampling points.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.31-34
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• 1987

A new efficientcoding system which can transmit video conferenceof viedeophone signals at a 64kbps is proposed. In addition to the interframe and CRC (Conditional Repleni shment Coding) system, BTVQ (Binary Tree searched Vector Quantizer)and RLC (Run Length Coding) methods are incorporated. Couble buffer memory is used for simple comtrol of channel symbol transmission and memory underflow And also buffer memory onerfolw is easily controlled by the thresholds of a MAD (Moving Area Betector)

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.442-460
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• 2001

In video-on-demand(VOD) systems it is important to minimize initial latency and memory requirements. The minimization of initial latency enables the system to provide services with short response time, and the minimization of memory requirements enables the system to service more concurrent user requests with the same amount of memory. In VOD systems, since initial latency and memory requirement increase according to the increment of buffer size allocated to user requests, the buffer size allocated to user requests must be minimized. The existing static buffer allocation scheme, however, determines the buffer size based on the assumption that thy system is in fully loaded state. Thus, when the system is in partially loaded state, the scheme allocates user requests unnecessarily large buffers. This paper proposes a dynamics buffer allocation scheme that allocates user requests the minimum buffer size in fully loaded state as well as a partially loaded state. This scheme dynamically determines the buffer size based on the number of user requests in service and the number of user requests arriving while servicing current requests. In addition, through analyses and simulations, this paper validates that the dynamics buffer allocation outperforms the statics buffer allocation in initial latency and the number of concurrent user requests that can be supported. Our simulation results show that, in proportion to the static buffer allocation scheme, the dynamic buffer allocation scheme reduces the average initial latency by 29%~65%, and in a systems having several disks. increases the average number of concurrent user requests by 48%~68%. Our results show that the dynamic buffer allocation scheme significantly improves the performance and reduce the capacity requirements of VOD systems.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.899-902
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• 2005

Pipeline hazard due to branch instructions is the major factor of the degradation on the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the branch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a tag memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single shared tag memory, we can expect the smaller ship size and the faster prediction. This hared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Journal of Digital Contents Society
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• v.12 no.2
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• pp.141-150
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• 2011

Recently the Solid State Drive (SSD) is widely used for storage system of various mobile devices. In this case, existing buffer replacement algorithms based on the hard disk do not consider characteristics of flash memory, so it caused performance degradation of the system. This paper proposes a novel buffer replacement policy called ABM (Asymmetric Buffer Management) policy. ABM policy separates read and write buffer space and applies different replacement unit and replacement algorithm for each buffer. In addition, write buffer delay scheme and dynamic size adaptation algorithm is applied for better performance. ABM outperforms other replacement policies, especially ABM-LRU-CLC shows 32% better performance than normal LRU policy.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.136-142
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• 2006

Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.