• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.173-174
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• 2007

Through Silicon Via ( TSV)는 향후3D integration devices (CMOS image sensors) 와 보다 더 직접화되고 진보된 memory stack에 기여 할 것이다. 이는 한층 더 진보된 microprocessors system 을 구축 하리라 본다. 해서 본문은 TSV plasma etching processing 소개와 특히 Bosch process에 대한 개선 방법을 제시하고자 한다.

• Journal of Information Display
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• v.4 no.4
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• pp.4-7
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Integration of gate circuit, transmission gate and level shifter was successfully performed in a large area display. Uniform and high performance of high quality grains of SLS technology make it possible to realize a uniform large size LTPS TFT-LCD with half the number of data driver IC's that is typically used in a-Si LCD. High aperture ratio of 65 % was achieved using an organic inter insulating method which lead to a high brightness of 500 cd/$cm^2$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.65-89
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• 2003

Next Highly sophisticated communication generation of the Advanced Electronics and Imaging processing society will require a vast information volume and super high speed signal transport and information instruction. This means that super high technology should be created for satisfying the demand. It's also required the high reliability of the communication system itself, It will be supported the new advanced packaging technology of the 3 Dimensional structured system and system integration technology. Here is introduced the new 3 Dimensional technology for IC nnd LSI packaging and Opt-electronics Packaging of ASET activity in Japan.

• Electronics and Telecommunications Trends
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• v.27 no.1
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• pp.51-60
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• 2012

실리콘 관통 홀(TSV) 기술은 2006년 삼성전자가 낸드 플래시 메모리에 적용하여 적층된 시제품을 선보인 이후 선풍적인 기술적 관심을 불러일으키고 있다. 그러나, 안타깝게도 CMOS 이미지 센서 모듈 외에는 실제로 양산에 적용되고 있는 사례가 매우 드물다. 이는 기술적으로, 그리고 상업적으로도 극복해야 하는 어려움이 많기 때문이다. 최근 Xilinx사는 28nm FPGA를 네 개의 작은 칩으로 분리하여 TSV가 있는 실리콘 인터포저 위에 2차원적으로 집적한 제품을 고객사들에게 선적하기 시작했다. 이와 같은 2.5D 집적 기술은 3D IC 집적 기술의 상용화를 위한 중간 단계로 여겨질 뿐만 아니라 그 자체로 독립적인 시장을 형성할 기술로도 판단되고 있다. 본고에서는 2.5D 집적을 위한 인터포저 기술개발 및 표준화 동향에 대해 소개하고자 한다.

• Korean Journal of Materials Research
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• v.20 no.6
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• pp.319-325
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• 2010

3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and $6.44\;J/m^2$ for 400, 450, and $500^{\circ}C$, respectively, in a $N_2$ atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.241-244
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• 2003

The world largest 21.3" LTPS LCD has been successfully developed using SLS crystallization technology. Successful integration of gate circuit, transmission gate and level shifter was performed in a large area uniformly. Uniformity and high performance from high quality grains of SLS technology make it possible to come true a uniform large size LTPS TFT-LCD with half number of data driver IC's used in typical a-Si LCD. High aperture ratio of 65% was obtained using an organic inter insulating method, which lead a high brightness of 500cd/cm2.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1269-1276
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• 2005

In this paper, Mixer using the direct-conversion method intended to use in front-end of a RF receiver is designed. The direct conversion Mixer is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for high integration, low power, and low cost. It operates at 2.4GHz band, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. Layout is implemented with a Mentor IC Station. The 2.4GHz CMOS Mixer employs a modified single-balanced Gilbert Cell with additional MOSFET in the output stages to improve IIP2, which is a standard of linearity in direct conversion receiver. Additional coversion-stages's transconductances are controlled by each MOSFET's physical properties. The HSPICE simulation results show that the 2.4GHz CMOS Mixer has voltage gam of 29dB, IIP2 of 63dBm, respectively. The Mixer also draws 3.5mA from a 3.3V supply.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.213-216
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• 2008

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.