Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Fabrication and Challenges of Cu-to-Cu Wafer Bonding

  • Kang, Sung-Geun (Microsystem Packaging Center, Seoul Technopark) ;
  • Lee, Ji-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Eun-Sol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Lim, Na-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Soo-Hyung (Microsystem Packaging Center, Seoul Technopark) ;
  • Kim, Sung-Dong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eun-Kyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
  • Received : 2012.03.02
  • Accepted : 2012.06.11
  • Published : 2012.06.30
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Abstract

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

Keywords

References

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