• 정보보호학회논문지
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• 제33권3호
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• pp.391-399
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• 2023

본 논문에서는 경량 블록 암호인 PIPO-64/128, 256에 대해 T-table을 사용한 구현을 최초로 제시한다. 제안 방법은 최초 16개의 T-table을 요구하지만, 필요한 두 종류의 T-table이 순환 구조임을 보이고 T-table 개수를 줄여 구현하는 변형 방법을 추가로 제시한다. 제안 방법들의 T-table 수(코드 크기)-속도간 상충관계 분석을 위해 각각 변형 구현물을 Intel Core i7-9700K 프로세서 환경에서 평가한다. 평가를 통해 획득한 속도 최적화 구현은 TLU(Table-Look-Up) 레퍼런스 구현에 비해 PIPO-64/128, 256에서 각각 11.33, 9.31배, 비트 슬라이스(Bit Slice) 레퍼런스 구현에 비해 각각 3.31, 2.76배 향상된 속도를 갖는다.

• ETRI Journal
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• 제22권1호
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• 대한전기학회논문지:전력기술부문A
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• 제53권6호
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• pp.316-323
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• 2004

This paper develops an ADWHM(Advanced Digital Watt-Hour Meter) which integrates and implements the voltage management data record function and the load management data record function in the electronic watt-hour meter. ADWHM is developed based on PIC16F874 which is 8bit micro-controller of RISK type for the easy of programing and maintenance, and electronic power signal processing module is located at front of it to reduce the computing load of processor. Also, a 16kbyte EEPROM is used to record the voltage management data and load management data for a week as well as watt-hour data and USART communication mode is used to transfer data from ADWHM to PC. The accuracy of the voltage and unt measuring for ADWHM is verified by identifying the LCD display values of the ADWHM after the voltage signals of id levels from digital function generator is applied to PT(Potential Transformer) and CT(Current Transformer) output under state which it is separated from real power line. On the its basic functions such as watt-hour data recording function, voltage management data recording function and load management data recording function was verified by showing data for three days among the collected data to PC by RS232C communication from ADWHM which was connected to real power lines for a week.

• 한국통신학회논문지
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• 제34권12C호
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• pp.1167-1176
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• 2009

본 논문에서는 OFDM(Orthogonal Frequency Division Multiplexing) 송신단에서 IFFT 를 수행한 후 Cyclic Prefix를 첨부하여 OFDM 심볼을 생성하는데 필요한 지연을 감소시킬 수 있는 IFFT(Time shifted DIT IFFT)의 구조를 제안하고, IEEE 802.16e Mobile WiMax OFDMA/TDD규격에 적합한, 1024크기의 FFT에 1/8 cyclic prefix를 가지는 시스템의 송신단 IFFT를 VHDL로 설계한 결과를 제시한다. 본 논문에서 제안하는 IFFT는 OFDM송신단의 지연을 줄이기 위하여 IFFT에 역비트(Bit-Reversed) 순서로 데이터를 입력하고, FFT의 Frequency Translation 특징을 이용해 IFFT의 출력이 cyclic prefix의 길이만큼 시간영역 쉬프트(Time-shift) 되어 나오도록 구현되었다. 이 과정은 cyclic prefix의 길이 특성을 이용하여 부가적인 복소곱셈기(Complex Multiplier)없이 구현되었고, OFDM 송신단의 지연과 함께 IFFT 결과를 저장하는 메모리의 크기도 줄일 수 있다. 송신단의 최종 출력이 통상적인 OFDM 심볼과 완전히 동일하기 때문에 전체 시스템의 성능에도 영향을 미치지 않는다.

• 제어로봇시스템학회논문지
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• 제13권2호
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• pp.154-162
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• 2007

In this paper, we propose a new AC-DC converter control method to comply with harmonics regulation(IEC 61000-3) effective for the inverter system of an air conditioner whose power consumption is less than 2,500W. There are many different ways of AC-DC converter control, but this paper focuses on the converter control method that is adopting an input reactor with low cost silicon steel core to strengthen cost competitiveness of the manufacturer. The proposed control method controls input current every half cycle of the line frequency to get unit power factor and at the same time to reduce switching loss of devices and acoustic noise from reactor. This kind of converter is known as a Partial Switching Converter(PSC). In this study, theoretical analysis of the PSC has been performed using Matlab/Simulink while a 16-bit micro-processor based converter has been used to perform the experimental analysis. In the theoretical analysis, electrical circuit models and equations of the PSC are derived and simulated. In the experiments, micro-processor controls input current to keep the power factor above 0.95 by reducing the phase difference between input voltage and current and at the same time to maintain a reference DC-link voltage against voltage drop which depends on DC-link load. Therefore it becomes possible to comply with harmonic regulations while the power factor is maximized by optimizing the time of current flow through the input reactor for every half cycle of line frequency.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제13권4호
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• pp.231-239
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• 2007

본 논문에서는 국내 표준 128비트 블록 암호화 알고리즘인 SEED를 하드웨어로 설계할 경우 면적-성능간의 trade-off 관계를 보여준다. 본 논문에서 다음 4가지 유형의 설계 구조를 비교한다. (1) Design 1 : 16 라운드 완전 파이프라인 방식, (2) Design 2 : 단일 라운드의 반복 사용 방식 (3) Design 3 : G 함수 공유 및 반복 사용 방식 (4) Design 4 : 단일 라운드 내부 파이프라인 방식. (1),(2),(3)의 방식은 기존의 논문들에서 제안한 각기 다른 설계 방식이며 (4)번 설계 방식이 본 논문에서 새롭게 제안한 설계 방식이다. 본 논문에서 새롭게 제안한 방식은, F 함수 내의 G 함수들을 파이프라인 방식으로 연결하여 면적 요구량을 (2)번에 비해서 늘이지 않으면서도 파이프라인과 공유블록 사용의 효과로 성능을 Design 2와 Design 3보다 높인 설계 방식이다. 본 논문에서 4가지 각기 다른 방식을 각각 실제 하드웨어로 설계하고 FPGA로 구현하여 성능 및 면적 요구량을 비교 분석한다. 실험 분석 결과, 본 논문에서 새로 제안한 F 함수 내부 3단 파이프라인 방식이 Design 1 방식을 제외하고 가장 throughput 이 높다. 제안된 Design 4 가 단위 면적당 출력성능(throughput)면에서 다른 모든 설계 방식에 비해서 최대 2.8배 우수하다. 따라서, 새로이 제안된 SEED 설계가 기존의 설계 방식들에 비해서 면적대비 성능이 가장 효율적이라고 할 수 있다.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2003년도 추계학술대회 논문집
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• pp.336-339
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• 2003

A digital data logging system has been developed for the purpose of a compact offline Ocean Bottom Seismometer(OBS). The Digital Data Logger(DDL) consists of A/D system, Micom with storage memory and firmware managing data files. The A/D system acquires data of 16bit/4ch with sampling rate of 250Hz per channel. The Micom, a micro controller board with T33521 processor of 8051 class, was equipped with 8 flash memories of 128MB for data storage capacity of 1GB. The firmware stores the acquiring data in form of binary files. The DDL was designated to be compact and light and to consume low energy as possible. The DDL is to interface with PC through USB(Universal Serial Bus). The performance of the DDL has been validated through tests with respect to a 3-axis seismometer.

• 제어로봇시스템학회논문지
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• 제9권2호
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• pp.117-123
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• 2003

Rotational machines such as optical disk drives, hard disk drives, and so on are subject to periodic disturbances caused by their mechanical characteristics. In the meanwhile, it is well known that repetitive control rejects periodic disturbance effectively. This paper presents a practical application of repetitive control to the track-following servo of an optical disk drive. The repetitive control system is composed of two repetitive controllers which compensate for periodic disturbances generated by track geometry and eccentric rotation of disk and a feedback controller stabilizing the feedback loop. A robust stability for all plant uncertainties is proved using linear matrix inequalities (LMIs). In the controller design, a weighting function is introduced for the feedback controller to ensure a minimum loop gain and a sufficient phase margin. The repetitive controllers and the feedback controller are designed by solving an optimization problem which can consider the robust stability condition and the system performance. The developed repetitive control system is implemented in the digital control system with a 16-bit fixed-point digital signal processor (DSP). Through simulation and experiment. The feasibility of the proposed repetitive control system is verified.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.353-359
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• 1988

In this paper, the design and implementation of a multi-processor based die bonder machine for the semiconductor will be described. This is a final research results carried out for two years from June, 1986 to July, 1988. The mechanical system consists of three subsystems such as bonding head module, wafer feeding module, and lead frame feeding module. The overall control system consists of the following three subsystems each of which employs a 16 bit microprocessor MC 68000 : (i) supervisory control system, (ii) visual recognition / inspection system and (iii) the display system. Specifically, the supervisory control system supervises the whole sequence of die bonder machine, performs a self-diagnostics while it controls the bonding head module according to the prespecified bonding cycle. The vision system recognizes the die to inspect the die quality and deviation / orientation of a die with respect to a reference position, while it controls the wafer feeding module. Finally, the display system performs a character display, image display ans various error messages to communicate with operator. Lead frame feeding module is controlled by this subsystem. It is reported that the proposed control system were applied to an engineering sample and tested in real-time, and the results are sucessful as an engineering sample phase.

• ETRI Journal
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• 제20권2호
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• pp.133-148
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• 1998

The objective of this paper is to present an adaptive algorithm for computing the weight vector which provides a beam pattern having its maximum gain along the direction of the mobile target signal source in the presence of interfering signals within a cell. The conjugate gradient method (CGM) is modified in such a way that the suboptimal weight vector is produced with the computational load of O(16N), which has been found to be small enough for the real-time processing of signals in most land mobile communications with the digital signal processor (DSP) off the shelf, where N denotes the number of antenna elements of the array. The adaptive procedure proposed in this paper is applied to code division multiple access (CDMA) mobile communication system to show its excellent performance in terms of signal to interference plus noise ratio (SINR), bit error rate (BER), and capacity, which are enhanced by about 7 dB, ${\frac{1}{100}}$ times, and 7 times, respectively, when the number of antenna elements is 6 and the processing gain is 20 dB.