A Single-Chip Video/Audio CODEC for Low Bit Rate Application

  • Park, Seong-Mo (Electronics and Telecommunications Research Institute (ETRI)) ;
  • Kim, Seong-Min (VLSI Architecture Team, ETRI) ;
  • Kim, Ig-Kyun (Electronics and Telecommunications Research Institute (ETRI)) ;
  • Byun, Kyung-Jin (Electronics and Telecommunications Research Institute (ETRI)) ;
  • Cha, Jin-Jong (VLSI Architecture Team, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Cho, Han-Jin (Integrated Circuit Design Research Department, ETRI)
  • 투고 : 1999.05.14
  • 발행 : 2000.03.31

초록

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

키워드

참고문헌

  1. ITU-T Recommendation Draft H.263, Video Coding for Low Bit Rate Communication
  2. Digital Image Compression Techniques Rabbani, Majid;Jones, Paul W.
  3. IEEE Consumer Elec. v.40 no.3 Design and Hardware Implementation of a Memory Efficient Huffman Decoding Hashemian, Reza
  4. IEEE Trans. Commun. v.COM-25 A Fast Computational Algorithms for the Discrete Cosine Transform Chen, W.H.;Smith, C.H.;Fralick, S.C.
  5. IEEE Trans. Acoust. Speech, Signal Processing v.ASSP-22 A New Hardware Realization of Digital Filters Peled, A.;Liu, B.
  6. IEEE Trans. Circuits Syst. v.CAS-34 A Concurrent Architechture for VLSI Implementation of DIscrete Cosine Transform Sun, M.T.;Wu, L.;Liou, M.L.
  7. ITC-CSCC'98 Processing v.I An Area Efficient Implementation of Zig-Zag and Quantzazation Buffer for H.263 Application Park, S.M.(et al.)
  8. 5th International Conference on VLSI and CAD Proceeding An Efficient Implementation of Run Length Coder for H.263 Application Park, S.M.(et al.)
  9. IEEE Trans. Commun. v.COM-29 Displacement Measurement and its Application Interframe Image Coding Jain, J.R.;Jain, A.K.
  10. IEEE Trans. Pattern Anal. Machine Intell. v.11 A Theory for Multiresolution Signal Decomposition: The Wavlet Representation Mallat, S.G.
  11. Commun. Pure Appl. Math. v.41 Orthnonormal Bases of Compactly Supported Wavelets Daubechies, I.
  12. Proc. IEEE v.83 Motion Estimation Technique for Digital TV: A Review and New Contribution Dufaux, F.;Moscheni, F.
  13. Proc. SPIE, Visual Commun. Image Processing v.1001 Displacement Estimation by Hierarchical Block Matching Bierling, M.
  14. ETRI Journal v.19 no.3 Design of chip for CDMA Mobile Station Yeon, Kwang-Il(et al.0
  15. ITU-T Recommendation G.723.1, Dual rate speech coder for Multimedia Communications Transmitting at 5.3 and 6.3 kbit/s
  16. CICC '95 Efficient DSP Design for Vocoder Application Yoo, H.Y.;Kim, J.J.;Byun, K.J.;Han, K.C.;Kim, D.K.;Kim, J.S.;Lee, H.B.;Bae, M.J.