• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.918-919
• /
• 2012

This paper present a method of function decomposition and input variable manipulation method based on modular design techniques. We obtain the column multiplicity of decomposition function according to row decomposition method. Also, the proposed partial decomposition function have advantage which is able to omit control function using t-Gate. We find the advantage for internal connection decrement 12% and T-gate number 16%, therefore we find the simple design circuit.

• Proceedings of the KIPE Conference
• /
• 2010.07a
• /
• pp.234-235
• /
• 2010

본 논문에서는 시간 분할 제어방식을 적용한 PDP 전원-구동 통합 시스템을 제안하였다. 제안 시스템은 하나의 전력변환회로를 시간에 따라 다르게 동작시킴으로써, 전원공급기능과 무효전력회수기능을 수행한다. 따라서 기존 방식인 전원회로와 구동회로를 별개로 사용하는 것에 비해 소자수 및 부피를 줄일 수 있으므로 저가형에 매우 적합하다. 본 논문에서는 기존 및 제안 시스템의 비교 분석과 실험을 통하여 제안 시스템의 특징 및 동작을 검증한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.5A
• /
• pp.682-687
• /
• 2000

EMI problem is very important in a printed circuit board design. This paper deals with image plane as one of the most effective method to reduce EMI in PCB. The shielding performance of one and two layers of image planes of finite width and length is analyzed by the method of moments based on the triangular surface patch model. The current distributions were modeled as two simple line sources. It is demonstrated that proper triangulation should be made so as to take two basis functions in the boundary triangles of the surface.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.4
• /
• pp.80-89
• /
• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Proceedings of the KIEE Conference
• /
• 2002.07b
• /
• pp.946-948
• /
• 2002

최근 컴퓨팅 기술의 발전으로 3차원 복합열전달(conjugate heat transfer) 문제를 계산하는 수 치해석 기술이 어느 정도 가능해 졌지만, 실제적인 전력기기 내부의 온도분포를 수치적으로 계산하는 것은 탑재된 구성요소의 다양한 크기와 형상으로 인한 매우 복잡한 경계조건을 수반하고 조밀한 격자를 요구하기 때문에 공학적이지 않다. 이를 위하여 해석적 모델을 수립하여 전력기기 열설계를 위한 수치적 해석에 적용하는 방법이 널리 사용되고 있다. 본 연구에서는 열회로망법(Thermal Network Analysis, TNA)을 이용하여 전력기기 내부의 온도분포를 예측할 수 있는 프로그램을 개발하였다. 전류가 흘러 열이 발생하고 소산되는 주회로 성분들을 각각의 노드로 분할하는 절차를 확립하였고 열접촉저항과 주울열을 적절히 선정함으로써 실제 전류가 흐르는 회로망 내 온도분포를 계산하였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10c
• /
• pp.37-39
• /
• 2001

본 논문은 여러 가지 데이터 압축 표준에서 채택하고 있는 이차원 이산 여현 변환과 그 역 변환 (DCT/IDCT)를 위한 효율적인 비동기식 행렬 벡터 곱셈기를 설계하였다. 본 논문에서 제안되어진 곱셈기는 일반적으로 DCT/IDCT의 입력 데이터가 대부분 zero입력이거나 또는 작은 비트수로 표현 가능하다는 점을 이용하여 저전력 고성능 동작을 구현할 수 있도록 설계하였다. 비동기식 설계 방식을 채택하여 Zero입력일 경우 곱셈과정을 생략하고, 정적 회로에 기초한 특정 계산 완료 인지 방식(Speculative Completion Sensing)와 비트 분할된 곱셈기를 이용하여 입력 비트 슬라이스에 대해 동적으로 회로의 계산부분을 활성화/비활성화를 동작을 할 수 있도록 설계되어졌다.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.125-128
• /
• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.9
• /
• pp.1442-1447
• /
• 1990

In this paper we propose the search algorithm of the boundary nodes that defined as the circuit segmentation when CUT is tested by pseudo-exhaustive testing. The algorithm treats the testability values of the nodes in CUT as the population composed of teh raw data, and after examines the level of significance a and then estimate the confidence interval of teh testability values. Thus One can easily searched the c9oundary nodes and PO of sub circuits. The proposed algorithm has been implemented under UNIX OS with C-language, applied to the combinational logic CUT. As a result, it is shown that the pseudo-exhaustive test patterns are least generated when \ulcornerhas 0.786. We confirmed that the rate of test pattern is 1.22%, compared with exhaustive test.

• Proceedings of the KIEE Conference
• /
• 2001.10a
• /
• pp.233-235
• /
• 2001

On the active filter converter for power factor correction is used inverter for a air-conditioner's power supply to meet IEC standard In the active filter topology for power factor correction, extra switch only control the input current indirectly to satisfied with the IEC standard for reducing the cost and size. In this paper, by dividing the input current into two different modes, the current conduction period can be widened and harmonics can largely be canceled between the two modes. Hence, the harmonics characteristics can be significantly improved, whereby the lower order harmonics, such as the fifth and seventh orders, are much reduced. The results are confirmed by theoretical and experimental implementations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.72-84
• /
• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.