• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.10-16
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• 2003

To analyze the effects of the air-bridge parasitic capacitances on the performance of coplanar waveguide pseudomorphic high electron mobility transistors (CPW PHEMTs), the gate-to-air-bridge ( $C_{ag}$ ) and the drain-to air-bridge ( $C_{ad}$ ) capacitances were taken into account plus the conventional pinched-off cold. FET circuit model. To examine the effects of the parasitic capacitances due to the air-bridges, a variety routing schemes for the air-bridge interconnection were adopted for fabricating the 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate length CPW HEMT's. According to air-bridge schemes, the $S_{21}$ gain is affected considerably. From the results of the fabricated CPW PHEMT, the $C_{ag}$ and $C_{ad}$ is one of the important factor of decreasing the gain of HEMTs.

• Composites Research
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• v.26 no.6
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• pp.337-342
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• 2013

The good dispersion of nano-materials in epoxy matrix was important parameter for the reinforcement effect, and the evaluation of dispersion degree was to prove it. This work was studied to predict the dispersion condition of nano-SiC powders in SiC/epoxy composites using capacitance measurement. Capacitance was defined to be the electric capacity in proportional to electron charge of the measuring section. In case of nano-SiC powders, the electron charge of SiC/epoxy composites was higher than that of neat epoxy resin. Capacitance was evaluated for each section of SiC/epoxy composites. The prediction of dispersion condition was verified by using capacitance measurement. Dispersion condition of nano-SiC powders in epoxy matrix was evaluated with two different dispersion methods, i.e., sonication and stirring methods. The dispersion degree was also verified with the tensile strength correlating to capacitance.

• Journal of IKEEE
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• v.22 no.1
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• pp.185-188
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• 2018

This paper describes the parasitic capacitance modeling according to the coil structure, section bobbin and winding method for hybrid choke coil with reduced parasitic capacitance capable of the EMI attenuation of broad bands from lower frequency to higher frequency applied in the EMI attenuation filter of LED-TV SMPS. Especially, the hybrid choke coil with reduced parasitic capacitance($C_p$) proposed in this paper can reduces the parasitic capacitance($C_p$) by adopting the winding methods of rectangular copper wire, compared to the conventional common mode choke coil with the winding method of automatic type. The first resonant frequency of the proposed hybrid choke coil has a tendency to increase as the parasitic capacitance is smaller and its impedance characteristics, especially in the high frequency bands, improves as the first resonant frequency increases. In the future, the proposed hybrid choke coil with reduced parasitic capacitance shows it can be actually utilized in not only LED-TV SMPS but also various applications such as LED Lighting, Note-PC Adapter, and so forth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.41-48
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• 2005

The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.83-88
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• 2003

This paper analyses a fault operation due to the effect of miller capacitance, which severely influences the performance of the IPMs based on computer-aided simulations, and also it presents a good solution to solve that problem. A miller capacitance existed between gate and collect is very closely related to the stray capacitance formed between gate and emitter, and the value of gate resistor. These relationships are proved by the computer-aided simulation. Based on the PSpice simulation results, a customized IPM employing an auxiliary circuit is presented to minimize a fault operation. And it is compared to the standard IPM by the experimental waveform. As a result, it is verified that a customized IPM has a voltage margin to prevent a fault operation approx. 3 [V].

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.07a
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• pp.357-358
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• 2013

본 논문에서는 커패시턴스를 이용해 수액 내에 있는 공기방울을 검출하고 수액의 성분을 구분 할 수 있는 측정기의 원리에 대해 제시해보려 한다. 이 측정기의 원리는 유전율의 변화를 감지하여 수액의 종류를 판단하고, 수액 내부의 기포를 검출해내는 등 의원성 사고를 근본적으로 막는 데에 그 의의가 있다. 실험결과 본 연구에서 제작한 측정기로 수액에 따른 값의 차이를 확인하였고, 발생한 기포에 대한 출력 결과를 확인할 수 있었다. 본 연구를 통해 커패시턴스 차폐의 정도가 결과의 신뢰도 측면에 중요한 요인으로 작용하고 있음을 확인 할 수 있었다. 향후 외부 간섭에 따른 노이즈에 대한 추가적인 커패시턴스 차폐 연구가 필요한 것으로 판단된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1349-1354
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• 2011

In this work, we fabricated the CdZnS/CdTe heterojunction and investigated the C-V characteristics to determine the depletion width and the charge density distribution. A parallel experiment on CdS/CdTe heterojunction was also carried out for comparison. The depletion region width, for CdZnS/CdTe heterojunction, was nearly constant, regardless of bias voltage. However, the depletion region was wider than that of CdS/CdTe heterojunction due to high resistivity of CdZnS film. The interface charge density of CdZnS/CdTe heterojunction was increased linearly with the bias voltage and showed lower values than those for CdS/CdTe junction. The open circuit voltage of CdZnS/CdTe heterojunction solar cells increased with zinc mole ratio due to reducing of the electron affinity difference between CdZnS and CdTe films. However, the increase of series resistance due to the high resistivity of Cd1-xZnxS films results in reducing conversion efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.175-184
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• 2016

In this paper, we propose the method to measure the capacitances using not LCR meter but capacitance to voltage(C/V) conversion. And we design the analog MUX circuits that convert 192 channels to 6 MUX channels in order to implement the diagnosis of multi-channel ultrasonic probe. This paper derives the conversion function that converts the digital voltage of each MUX channel to the capacitance using the least squares method because the circuit characteristics that convert the voltage of each MUX channel to the capacitance are different. The developed prototype illustrates the performance test results that the measure times are measured by within 4sec and the measure error rates of maximum, minimum, and average values are within 5% in terms of the repeated measurements of all 192 channels.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.4
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• pp.350-357
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• 2016

In this paper, a small mu-zero zeroth order resonance(ZOR) antenna based on meta structure is proposed using parasitic patch at 5.8 GHz. The mu-zero ZOR antenna is designed by utilizing the resonance of series inductance and capacitance of mu-negative transmission line and its size can be further reduced by a simple parasitic patch. The parasitic patch can increase series capacitance of mu-negative transmission line related to a resonant frequency. We have simulated and optimized dimension of the parasitic patch using Ansys commercial simulator(HFSS). As a result, the antenna has the following characteristics: kr of 0.59, efficiency of 92 %, and gain of 6.57 dBi. Also, its size is reduced by 24 % compared to a conventional mu-zero ZOR antenna. The measured results are in good agreement with the simulated results.