• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1250-1252
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• 2003

This Paper presents Sigma-Delta Modulation(SDM) schemes to generate switching waveform for a high-power factor boost-type rectifier. The SDM scheme can be implemented by simple digital algorithm unlike conventional PWM schemes with several hardware, and has the characteristics of spectrum-spreading and noise-shaping effects, which are profitable in harmonic reduction of input current in the boost-type rectifier. The comparison results of their spectrum performances shows that the 1st-order SDM has better harmonic suppression effect than conventional PWM scheme and Dithered SDM scheme.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.152-155
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• 2000

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution A/D conversion in a VLSI technology. Because high-order noise shaping great]y reduces the quantization noise in the signal band. This paper introduces a third-order cascaded sigma-delta modulator that is stable for large input level. Modulator was simulated 3.3V single power supply voltage in 0.65$\mu\textrm{m}$ CMOS technology. It achieves 80㏈ SNR for a 20㎑ input signal bandwidth. A lock frequency is 3㎒ that is 80 oversampling ratio.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.982-985
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• 1999

An efficient technique to trade off speed for resolution is the sigma-delta modulation (SDM). This paper proposes a new SDM architecture to improve conversion rates and SNR(Signal-to Noise Ratio) by using master clock and four divided clock. The charateristics of the proposed SDM are simulated in MATLAB environment. and optimizing the capacitor sizes is done by iterative processing. other analog characteristics are simulated using 0.65${\mu}{\textrm}{m}$ n-well CMOS process, double poly and single metal. The result of simulation shows that more increasing the effective bits of internal ADC/DAC, bigger the improvement of SNR.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.513-519
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• 2001

This paper proposed a random sigma-delta modulator(RSDM), which is constructed by a 1st order sigma-delta modulator(SDM) and a simple structured random binary generator(RBG). The 1st order SDM produces a switching pulse waveform which has the same low-frequency component as the reference input, while the RBG spreads the distribution of the number of sampling per switching cycle, and thus disperses the spectrum spikes in the output. The relationship between the harmonic spectra and the number of sampling per switching cycle is studied through computer simulations, and the frequency spectra of the RSDM are confirmed in an experimental setup.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.