• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.422-429
• /
• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.4
• /
• pp.913-920
• /
• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of agriculture & life science
• /
• v.44 no.4
• /
• pp.69-77
• /
• 2010

Fuzzy control is widely used for improving temperature control performance as controlling ventilation in greenhouse because the technique can respond more flexibly to the outside air temperature and wind speed. By pre-studied PID and normal fuzzy control this study was performed to obtain the fundamental data that can be established in better greenhouse ventilation control method. The temperature control error by the simple fuzzy control was $1.2^{\circ}C$. The accumulated operating size of the window and the number of operating were 84% and 13, respectively. These showed equivalent control performance with pre-studied result that control error. The accumulated operating size of the window and the number of operating were 75% and 12, respectively. The proposed fuzzy technique was simple control logic method compared with step and PID control methods, but it showed equivalent performance. Therefore, the proposed simple fuzzy control method could be used in micro controller of small programmable memory size and many applications.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.7 no.3
• /
• pp.27-33
• /
• 1993

This paper presents the &tal controller for driving high frequency voltage fed PWM inverter that carrier frequency is over 2OkHz.We analyzed the conventional PWM to select a proper PWM pattern. as the result, obtained PWM pattern of the controller in which asynchronus staircase sinusoidal waveform is used as reference signal, and variable carrier ratio method was used for PWM control. The PWM controller is designed by fully digital method. Especially, Thk proposed controller is consisted of 8 bit one-chip microprocessor and digital logic. the former is for arithmetic and data processing, and the latter is for PWM pattern synthesis. Therefore, The responsibility and controllability is improved. Also, Data processing capability is improved using proper program to output modulation index with 9 bits. Circuits configuration of digital controller are made up of one chip 8051 and EPLD, and its controllability is tested by operating voltage fed inverter. Harmonics and current waveform is evaluated and analyzed for the voltage fed inverter system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.11
• /
• pp.2541-2547
• /
• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• The Journal of the Acoustical Society of Korea
• /
• v.18 no.2
• /
• pp.53-60
• /
• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.180-184
• /
• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.15 no.5
• /
• pp.91-103
• /
• 2015

This paper presents "The 3-User NOR switching channel based on interference decoding with receiver cooperation" in succession to "Jeju Jong Nang channel code I, II". The Jeju Jong Nang code is considered as one of the earliest human binary coded communication (HBCC) in the world with a definite "1" or "0" binary symbolic analysis of switching circuits. In this paper, we introduce a practical example of interference decoding with receiver cooperation based on the three user Jong Nang NOR switching channel. The proposed system models are the three user Jong Nang (TUJN) NOR logic switching on-off, three-user injective deterministic NOR switching channel and Gaussian interference channel (GIC) with receiver cooperation. Therefore, this model is well matched to Shannon binary symmetric and erasure channel capacity. We show the applications of three-user Gaussian interference decoding to obtain deterministic channels which means each receiver cooperation helps to adjacent others in order to increase degree of freedom. Thus, the optimal sum rate of interference mitigation through adjacent receiver cooperation achieves 7 bits.

• Journal of IKEEE
• /
• v.12 no.1
• /
• pp.59-64
• /
• 2008

In this paper, a new efficient SMPS has been designed and implemented. It can replace the existing product that is widely used in industry. To investigate the performance of the conventional SMPS, the output voltage changes due to variations in the input voltage and the load conditions, and the ripple and noise voltages have been measured and analyzed. As a result, it has been confirmed that the noise in the conventional SMPS is severe due to the deficiency of patterns for current. This is because the conventional SMPS draw out all outputs using one transformer and the alarm logic exists in the output path. To solve this problem, the switching frequency is increased from 17KHz to 70KHz and the current patterns are fully guaranteed by separating the alarm circuit and PWM circuit as a sub-board from the main board. Measurement results shows that the output noise of the designed SMPS decreases below 32% of the conventional SMPS noise for various test conditions, and both the line and load regulations are improved.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.4 s.310
• /
• pp.73-79
• /
• 2006

Due to the powerful correcting performance, turbo codes have been adopted in many communication standards such as W-CDMA(Wideband Code Division Multiple Access), CDMA2000, etc., and implemented by hardware in many kind of fields. Although several hardware structures and improved algorithm have been proposed, these problems such as hardware area, operating speed and power consumption are still a major issue to be solved in practical implementations. In this paper, we designed the turbo-code decoder using MAX -SCALE operation derived from the posterior probability optimization. The proposed circuit has been measured their performance on Matlab and MaxPlusII and implemented on the FPGA As a result, when implementing the proposed algorithm on the FPGA, this circuit only occupies 616 logic elements. And comparing the performance with the MAP(Maxirnum a Posteriori) decoding algorithm, the operating speed was increased by about 40%(56.48MHz) and BER(Bit Error Rate) was increased by 6.12.