An Implementation of Turbo -Code Decoder using Posteriori Probability Optimization

사후확률 최적화를 이용한 터보코드 복호기 구현

  • Noh Jin-Soo (Dept. of Electronic Engineering, Chosun University) ;
  • Rhee Kang-Hyeon (Dept. of Electronic Engineering, Chosun University)
  • Published : 2006.07.01

Abstract

Due to the powerful correcting performance, turbo codes have been adopted in many communication standards such as W-CDMA(Wideband Code Division Multiple Access), CDMA2000, etc., and implemented by hardware in many kind of fields. Although several hardware structures and improved algorithm have been proposed, these problems such as hardware area, operating speed and power consumption are still a major issue to be solved in practical implementations. In this paper, we designed the turbo-code decoder using MAX -SCALE operation derived from the posterior probability optimization. The proposed circuit has been measured their performance on Matlab and MaxPlusII and implemented on the FPGA As a result, when implementing the proposed algorithm on the FPGA, this circuit only occupies 616 logic elements. And comparing the performance with the MAP(Maxirnum a Posteriori) decoding algorithm, the operating speed was increased by about 40%(56.48MHz) and BER(Bit Error Rate) was increased by 6.12.

터보 코드는 강력한 에러정정 성능 때문에 W-CDMA(Wideband Code Division Multiple Access), CDMA2000 등의 통신 알고리즘에 적용되고 있으며, 여러 분야에서 하드웨어로 구현되어졌다. 여러 가지의 개선 알고리즘과 하드웨어 구조가 제안되어 졌으나 아직까지 하드웨어 면적, 동작속도 및 소비전력 등의 문제가 연구되어지고 있다. 본 논문에서는 하드웨어 면적과 동작속도를 향상시키기 위하여 사후확률 최적화로부터 유도된 MAX-SCALE 알고리즘을 이용한 터보코드 복호기를 설계하였으며, 제안된 회로는 Matlab과 MaxPulsII를 사용하여 성능 측정 및 FPGA 보드상에 구현되었다. 결과적으로 제안된 구조를 사용하여 FPGA에 구현했을 때, 616개의 로직 요소 (Logic Element)를 가지며 MAP(Maximum a Posteriori) 복호 알고리즘에 비해 동작속도는 56.48MHz로 약 40% 향상되었으며, 6.12%의 BER(Bit Error Rate) 성능이 향상되었다.

Keywords

References

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