• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.132-139
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• 2016

In the bandpass sampling(BPS), the sampling frequency for the analog-to-digital converter is lower than that of the signal to be sampled. Since the BPS operation results in the signal spectrum to be copied on the baseband, it is possible for the frequency down-converter to be conveniently omitted. The second-order BPS system is introduced in order to cancel the aliased interference components from the BPS output that may be generated by the BPS processing. In this paper, we introduce a design method for the optimal phase of the interpolant filter in the second-order BPS system which enables to maximally cancel the aliased components. Being mathematically derived, this method can always be applied independently to the spectral characteristics of the BPS input signal. The performance improvements by the suggested method has been measured statistically with various power spectra of the received signal, and it has been shown that the maximal amount of the improvements reaches up to 5~20 [dB] in comparison with the previous suboptimal algorithm.

• Journal of Digital Convergence
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• v.13 no.4
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• pp.137-146
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• 2015

The aging process in this country is underway at the fastest pace compared to those of the leading countries. On the other hand, preparing for retirement funds is more difficult than before due to the impact of slow interest rate and slow growth. The purpose of this study is to examine the necessity of providing various financial services in preparation for the future aging era. After analizing the various materials and utilizing a survey of the bank employees and the general public, we have found the followings. The replacement rate of this country, 55%, is much lower than the suggested level of World Bank, 75%. Also, the pension ratio in the income after retirement of this country is much lower compared to those of the States and Japan. The most people who participated in the survey needed ￦2,000 - ￦2,990 thousand for monthly living expenses after retirement. For the retirement funds, the higher the age the higher proportion of savings deposits they want, and the lower the age the higher proportion of insurance and pension products they want. Based on these analyses, the necessities of developing financial life planning which includes both financial and non-financial sides, retirement funds management according to age, revitalization of housing pension and developing diverse retirement funds are suggested.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• KIISE Transactions on Computing Practices
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• v.21 no.6
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• pp.430-435
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• 2015

IP-based, next generation digital broadcast systems transmit DASH segment files. Designed by the DASH system, DASH segment files provide variable quality of contents, while the size of DASH segment files varies even if the file has the same quality. Delays and inefficient use of resources are major challenges in the transmission of variable size DASH segment files in broadcasting systems. Traditional broadcasting transmission systems are designed according to characteristics of physical layer of broadcast, and thus, delay and inefficient resources use is difficult to find. Yet, transmission content quantities continue to rise in the next-generation broadcasting systems (e.g. FHD, UHD (4k, 8k)) with variability of the segments file size as well. Resources for next-generation broadcast are more abundant than traditional broadcast with recent development, but continue to be limited and fixed. Resource delay and inefficiency are important but has not been extensively studied. We propose a transmission structure solution to analyze the delay and efficiency of the resource as each DASH segment file is transmitted, and have further performed simulation studies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of Digital Contents Society
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• v.15 no.3
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• pp.439-447
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• 2014

This study seeks to validate the development and the effectiveness of a web-based online education program used to enhance communication skills of college students. Communication skills are important skills demanded of college students seeking employment that play a significant role in self-introduction, presentations, interviews, and continuous interaction in the workplace. 105 students in the third and fourth year of D University were selected for the experimental and control groups in which the experimental group met once a week for one semester in 2013 for a total of 16 weeks(twenty minutes) while the control group was left untreated. The variable of effectiveness for the results of this study was based on the criteria of communication and performance behavior skills. The results show that the communication skills and performance behavior skills proficiency of the experimental group compared to the control group, have made dramatic improvements. Therefore, the web-based communication skills training program for college students was found to be effective in the enhancement of the communication skills of college students. For the future, we expect further sustained development of various effective capabilities programs along with the promotion of web-based online education.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.54-61
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• 2007

In this paper, on-demand service streaming protocol for user-created contents in digital cable broadcasting environment is considered. In order to provide variety media contents service like UCC in digital cable broadcasting environment, the same service model as RVOD(Real Video on Demand) is required and the different interface for each broadcasting platform is needed in a current OCAP environment. Using return path based RTP, we separate existing VOD stream band into broadcasting and VOD stream band. In order to broaden On-demand service, consistent expansion of the infrastructure same as live broadcasting system is inefficient in the digital cable broadcasting environment. Using existing network protocol, the service which is insensitive to the infrastructure for VOD service becomes possible. Therefore we considered the analysis of the class of download available structure in the Set-Top-Box for RTP(Real-time Transport Protocol) and designing the decoding available streaming server for UCC transcoding and transmission in the receiver. Designing a efficient VOD service and system under the broadcasting environment gives a expansion of On-Demand service and more chance to upload and utilization of contents.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.19-27
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• 1998

The Transmitter part of single RF transceiver chip for an extended GSM handset application was circuit-designed, fabricated adn evaluated. The RF-IC Chip was processed by 0.8${\mu}m$ Si BiCMOS, 80 pin TQFP of $10 {\times} 10mm$ size, 3.3V operated RF-IC reveals, in general, quite reasonable integrity and RF performances. This paper describes development resuts of RF transmitter section, which includes IF/RF up-conversion mixer, IF/RF polyphase and pre-amplifier. The test results show that RF transmitter section is well operated within frequency range of 880~915MHz, which is defined on the extended GSM(E-GSM) specification. The transmitter section also reveals moderate power consumption of 71mA and total output power of 8.2dBm.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.9-18
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• 1998

A single RF transceiver chip for an extended GSM handset application was designedm, fabricated and evaluated. A RFIC was fabricated by using silicon BiCMOS process, and then packaged in 80 pin TQFP of $10 {\times} 10 mm^{2}$ in size. As a result, it was achieved guite reasonable integraty and good RF performance at the operation voltage of 3.3V. This paper describes development results of RF receiver section of the RFIC, which includes LNA, down conversion mixer, AGC, switched capacitor filter and down sampling mixer. The test results show that RF receiver section is well operated within frequency range of 925 ~960 MHz, which is defined on the extended GSM specification (E-GSM). The receiver section also reveals moderate power consumption of 67 mA and minimum detectable signal of -105 dBm.