• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1190-1196
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• 2014

This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

• Aerospace Engineering and Technology
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• v.11 no.1
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• pp.158-168
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• 2012

This paper deals with TVC nozzle stroke verification test and corresponding analysis techniques related to kick motor TVC system of KSLV-I second stage. It is shown that the relationship between TVC stroke and potentiometer voltage is revealed via the open-loop stroke verification test, and other major operational parameters including nozzle alignment error, actuation error, neutral position, radius of nozzle rotation, location of nozzle rotation center, angle conversion coefficients, etc. are analyzed via the closed-loop stroke verification test. The TVC stroke verification test results for the first and second flight model of KSLV-I show that all TVC operational parameters of KSLV-I second stage were normally setup for the first and second flight tests.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.1
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• pp.80-83
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• 2017

In this paper, the X-band reconfigurable frequency selective surface having flexible geometry was proposed. The proposed RFSS is composed of patterns of cross-shaped loop with inductive stub, which can control the frequency response for C-Band and X-band by ON/OFF state of PIN diode. To minimize the parasitic effect and to obtain the high level of isolation between the unit cell of FSS and the bias circuit, we designed the grid type bias line on bottom layer through via hole. The measured transmission characteristics show good agreement with the simulation results and good stability of frequency response for different incident angles and curvatures of surface.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.139-147
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• 1999

In this paper, we present the new angular velocity pick-off method for DTG (dynamically tuned gyroscope) which is widely used in various inertial navigation systems and motion control systems. In case of the external angular velocity input, the proposed scheme can make a smaller tilt-angle rather than that of conventional PI method in the transient and steady state because it has an additional inner rebalance loop with a mathematical model of the real gyroscope. So, without any mechanical redesign of the DTG, its dynamic range can be enlarged by the proposed method. The theoretical analysis and simulation model of DTG with the proposed scheme are given. Finally, the proposed scheme is verified.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1325-1332
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• 2009

In this paper, we design a 2.4 GHz bio-radar system that can detect human heartbeat and respiration signals with small size and improved noise performance using single circular-polarized antenna and phase-locked loop. The demonstrated bio-radar system consists of single circular-polarized antenna with $90^{\circ}$ hybrid, low-noise amplifier, power amplifier, voltage-controlled oscillator with phase-locked loop circuits, quadrature demodulator and analog circuits. To realize compact size, the printed annular ring stacked microstrip antenna is integrated on the transceiver circuits, so its dimension is just $40\times40mm^2$. Also, to improve signal-to-noise-ratio performance by phase noise due to transmitter leakage signal, the phase-locked loop circuit is used. The measured results show that the heart rate and respiration accuracy was found to be very high for the distance of 50 cm without the additional digital signal processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.613-619
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• 2017

In this paper, DF(Dual Fuel) Generator modeling, which uses both conventional diesel fuel and LNG fuel, has been performed and monitoring system has been developed based on MATLAB/SIMULINK for the development of PMS(Power Management System) HILS(Hardware In the Loop Simulation). The principal components modeling of DF Generator are DF engine which provides the mechanical power and synchronous generator which convert the mechanical power into electrical power. Submodels, such as throttle body, intake manifold, torque generation and mass of LNG and diesel Quantity are used to perform DF engine. Also, governor is used for load sharing between paralleled DF generators to share a total load that exceeds the capacity of a single generator. To verify modeling of DF Generator designated ship lumped load Simulation is carried out. A validity of DF Generator has been verified by comparison between simulation results and estimated result from the designated lumped load.