• Electrical & Electronic Materials
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• v.9 no.6
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• pp.626-631
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• 1996

현재 선진국에서는 전자기기에서 복사되는 전자파 및 이에 노출되었을 때의 내성에 대해서 동시에 규제하고 있다. 따라서 전자기기에서 사용하는 신호의 주파수가 점점 높아지고 회로가 집적화되므로 회로설계에 포함되지 않는 기생 소자의 영향도 연구되어져야 한다. 그러므로 이러한 조건을 모두 고려하여 초고주파 회로를 완전하게 설계제작할 수 있다면 이는 이상적인 기술이라 할 수 있을 것이다. 이것을 이루려면 많은 시간 동안의 연구와 분석을 통해 최종 생산물이 되기까지 대단한 노력이 요구된다. 본문에서는 초고주파 인쇄 회로 기판을 설계할 때 고려해야 할 점, 즉, 유전율 및 유전체의 두께, 소자 실장, 접지면 부착 및 회로의 패키지화에 관해서 소개하고자 한다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.12
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• pp.3244-3256
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• 1998

집적회로가 고집적화 그리고 고성능화 되어지면서 설계된 레이아웃의 전기적 연결 관계와 회로 성능을 검증할 필요성이 더욱 강조되고 있다. 본 논문에서는 레이아웃으로부터 소자의 기하학적인 모델 파라미터와 기생 저항과 커패시턴스 등을 포함하는 회로 정보를 추출하기 위하여 레이아웃 내의 모든 배선에 대한 도형을 방향성 변을 사용하여 독립된 다각형 블록의 집합으로 기술하고, 이 블록과 소자의 인접여부에 의해 MOS 트랜지스터와 전기적 연결 관계를 찾아서 회로를 추출할 수 있는 새로운 알고리즘을 제안한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.2
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• pp.14-21
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• 1981

This paper describes a method for realizing RC active filters, by the use of the CGIC's In realizing the CGIC circuit, every element in the circuit is selected so as to minimize the effect of the non -ideal characteristic of operational amplifers, and an extra element is added to the, CGIC circuit to compensate the parasitic capacitances of the circuit. The CGIC s are utilized in the design of active filters using ladder embedding technique. The design procedure is presented in detail and the application is illustrated by the design of a band-pass filter of high order.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1082-1088
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• 2006

A turnstile antenna using the parasitic monopole has been developed for STSAT-2 TT&C application. The antenna consists of two radiating elements; a bow-tie dipole and a parasitic monopole. The bow-tie dipole is main radiating element, used a bow-tie structure for bandwidth improvement and size reduction. The parasitic monopole improved beamwidth and axial ratio. The input impedance of the antenna is about 50 ohm without a matching circuit. The proposed antenna has beamwidth of $>140^{\circ}$, axial ratio of < 3 dB and VSWR of < 1.5 in the band of $2.075{\sim}2.282GHz$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.13-15
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• 2004

The current driven in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure play a significant role and degrade the device performance. These other resistances need to be less than 15％ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.36-46
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• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

• Journal of IKEEE
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• v.26 no.3
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• pp.520-523
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• 2022

In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

• Journal of IKEEE
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• v.25 no.4
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• pp.735-740
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• 2021

In this paper, we propose a new ESD protection device with high holding voltage with low current gain of parasitic NPN BJT by improving the structure of the existing LTDDSCR. The electrical characteristics of the proposed protection device were analyzed by HBM simulation using Synopsys' TCAD simulation, and the operation of the added BJT was confirmed by current flow, impact ionization and recombination simulation. In addition, the holding voltage characteristics were optimized with the design variables D1 and D2. As a result of the simulation, it was verified that the new ESD protection device has a higher holding voltage compared to the existing LTDDSCR and has a symmetrical bidirectional characteristic. Therefore, the proposed ESD protection device has high area efficiency when applied to an IC and is expected to improve the reliability of the IC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.730-738
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• 2009

In this paper, we present a equivalent circuit considered parasitic elements about LTCC multi-layer BPF structure that was studied previously and a process of extraction of the element value using SOC technique. By applying extracted element values to equivalent circuit, 2th LTCC filter was designed and fabricated that was applied to satellite DMB. The filter was fabricated of Dupont951 substrate with relative permittivity of 7.8, the dimension of the fabricated filter is $2.4{\times}3.8{\times}0.378mm^3$. The measurement results indicate 1.4 dB of insertion loss and 32.3 dB of return loss, which are in good agreement with simulated ones.