• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1532-1535
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• 2013

변환 블록은 영상 압축에서 데이터를 공간적 영역에서 주파수 영역으로 변환해줌으로써 압축의 효율성을 높이는 역할을 수행한다. 본 논문에서는 고성능 HEVC를 위한 4개의 TU 모드($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$)를 지원하는 변환 블록 하드웨어 구조를 제안한다. 제안하는 변환 블록의 하드웨어 구조는 공통 연산기를 사용하여 각 TU 모드에 맞는 행렬 계수들 간의 연산을 수행한다. 또한 병렬적인 구조로 설계하여 $4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$ 크기 TU 모드의 행렬 연산을 처리하는 사이클수가 35cycle로 동일하게 처리된다. TSMC 180nm CMOS 공정 라이브러리를 통해 합성한 결과 $4k(3840{\times}2160)@30Hz$의 영상을 기준으로 최대 동작주파수는 400MHz이고 총 게이트 수는 159k이며, 10-Gpels/cycle의 처리량을 갖는다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.37-42
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• 2008

In H.264/AVC decoder, intra predictor, motion compensator, and deblocking filter need to read reference images in external frame memory in decoding process. They read external frame memory very frequently, which lowers system operation speed and increases power consumption. This paper proposes a intra predictor integrated with motion compensator without external frame memory. It achieves power reduction and memory bandwidth minimization by exploiting data reuse of common and repetitive pixels. The proposed infra predictor achieves more than $45%\;{\sim}\;75%$ cycle time reduction compared with conventional intra predictors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.416-419
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• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• School Mathematics
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• v.17 no.1
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• pp.119-134
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• 2015

The purpose of this study was to specify knowledge and skills that are expected to be learned by students worldwide at the elementary level of Mathematics. This was achieved by extracting knowledge and skills commonly expected to know and perform in elementary school level by analyzing elementary math curriculum of twelve countries that vary geographically and economically. Based on the data gathered and analyzed, the common domains extracted from this study in elementary level Mathematics include Number and Operations, Geometry, Measurement and Data. And knowledge and skills that children are expected to achieve in each domain by the end of primary school were listed. This research showed that for elementary level Mathematics, the majority of the curricula had the commonalities in Number and Operations, Geometry, Measurement and Data. Though this study had the limitations of analyzing curriculum documents open to public, this study will offer the ground for discussion on the elementary mathematics education in a global context.

• The Journal of the Acoustical Society of Korea
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• v.25 no.3
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• pp.113-120
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• 2006

This paper is concerned with a equalization technique for Orthogonal Frequency Division Multiplexing (OFDM) systems based on a block type pilot arrangement over slow fading channels. The bit rates obtained in underwater channels are relatively modest compared to some other communication channels such as cellular phones or indoor wireless systems. Consequently. the Doppler effect is the important parameter in tracking a channel. In case of a coherent demodulation scheme, the residual mean phase errors due to Doppler frequency may be fatal for the performance of the system. The equalizer could not solely handle mean Doppler shift. To account for the common Doppler effect a phase error tracking loop is used with the frequency equalizer. so that the rotation errors are avoided. Furthermore. simulations show that we can reduce the computational load of the tracking loop with negligible effect on performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.830-836
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• 2006

In this paper described an auto tuning neuro-fuzzy PID controller based neural network. The PID type controller has been widely used in industrial application due to its simply control structure, easy of design, and inexpensive cost. However, control performance of the PID type controller suffers greatly from high uncertainty and nonlinearity of the system, large disturbances and so on. In this paper will design to take advantage of neural network fuzzy theory and pid controller auto toning technique. The value of initial scaling factors of the proposed controller were determined on the basis of the conventional PID controller parameters tuning methods and then they were adjusted by using neural network control techniques. This controller simple structure and computational complexity are less, and also application is easy and performance is excellent in system that is strong and has nonlinearity to system dynamic behaviour change or disturbance. Finally, the proposed auto tuning neuro-fuzzy controller is applied to magnetic levitation. Simulation results demonstrated that the control performance of the proposed controller is better than that of the conventional controller.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.499-508
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• 1995

Domain Analysis is an activity to identify commonalities and variabilities which similar application areas in order to reuse analyzed information easily in new software construction. Most of domain analysis output is represented by various diagrams without common standard, and its manual reuses result in low reusability. Domain analysis language can be used to represent domain analysis information and make it possible to automate reuse and test the specifications. In this paper we designed and implemented a processor to reuse domain analysis information represented by domain analysis language and applied our approach to a rental domain and got new specification instances. In addition, we compared reuse of a data flow diagramming tool with reuse of a domain information processor and found combining and found combining of each approach can increase the reusability of both.

• The Journal of the Acoustical Society of Korea
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• v.7 no.4
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• pp.31-53
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• 1988

In this work we study extensively the structures and performance characteristics of the block least mean-square (BLMS) adaptive digital filters (ADF's) that can be realized efficiently using the fast Fourier transform (FFT). The weights of a BLMS ADF realized using the FFT can be adjusted either in the time domain or in the frequency domain, leading to the time-domain BLMS(TBLMS) algorithm or the frequency-domain BLMS (FBLMS) algorithm, respectively. In Part Ⅰof the paper, we first present new results on the overlap-add realization and the number-theoretic transform realization of the FBLMS ADF's. Then, we study how we can incorporate the concept of different frequency-weighting on the error signals and the self-orthogonalization of weight adjustment in the FBLMS ADF's , and also in the TBLMS ADF's. As a result, we show that the TBLMS ADF can also be made to have the same fast convergence speed as that of the self-orthogonalizing FBLMS ADF. Next, based on the properties of the sectioning operations in weight adjustment, we discuss unconstrained FBLMS algorithms that can reduce two FFT operations both for the overlap-save and overlap-add realizations. Finally, we investigate by computer simulation the effects of different parameter values and different algorithms on the convergence behaviors of the FBLMS and TBLMS ADF's. In Part Ⅱ of the paper, we will analyze the convergence characteristics of the TBLMS and FBLMS ADF's.