• Title/Summary/Keyword: $V_{th}$

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The Analysis of Retention Characteristic according to Remnant Polarization(Pr) and Saturated Polarization(Ps) in 3D NAND Flash Memory (3D NAND Flash Memory의 Remnant Polarization(Pr)과 Saturated Polarization(Ps)에 따른 Retention 특성 분석)

  • Lee, Jaewoo;Kang, Myounggon
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.329-332
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    • 2022
  • In this paper, retention characteristics of lateral charge migration according to parameters of 3D NAND flash memory to which ferroelectric (HfO2) structure is applied and ∆Vth were analyzed. The larger the Ps, the greater maximum polarization possible in ferroelectric during Programming. Therefore, the initial Vth increases by about 1.04V difference at Ps 70µC/cm2 than at Ps 25µC/cm2. Also, electrons trapped after the Program operation causes lateral charge migration over time. Since ferroelectric maintains polarization without applying voltage to the gate after Programming, regardless of Ps value, polarization increases as Pr increases and the ∆Vth due to lateral charge migration becomes smaller by about 1.54V difference at Pr 50µC/cm2 than Pr 5µC/cm2.

V&V of Integrated Interoperability System for LVC Simulation on Aircraft Weapon System (항공무기체계 LVC 시뮬레이션을 위한 통합연동시스템 V&V)

  • Oh, Jihyun;Jang, Young Chan;Kim, Cheon Young;Jee, Cheol Kyu;Hong, Young Seok
    • Journal of the Korea Institute of Military Science and Technology
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    • v.18 no.3
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    • pp.326-334
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    • 2015
  • This paper describes the verification and the validation about the development of the integrated interoperability system for live, virtual, and constructive simulations on the aircraft weapon system. The proposed integrated interoperability system provides the framework and application softwares for implementing a synthetic environment emulating real-world environment among distributed simulation models, which are a mission model and an air combat model of a constructive level, an tactical simulator of a virtual level, and simulated ACMI of a live level. In this paper, we verify requested functions through an developmental test and evaluation, and validate operability and usability through conducing integrated LVC scenarios on the integrated interoperability system.

Threshold voltage shift of solution processed InGaZnO thin film transistors with indium composition ratio (용액 공정으로 제작된 InGaZnO TFT의 인듐 조성비에 따른 문턱전압 변화)

  • Park, Ki-Ho;Lee, Deuk-Hee;Lee, Dong-Yun;Ju, Byung-Kwon;Lee, Sang-Yeol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.3-3
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    • 2010
  • We investigated the influence of the indium content on the threshold voltage ($V_{th}$) shift of sol-gel-derived indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs). Surplus indium composition ratio into IGZO decreases the value of $V_{th}$ of IGZO TFTs showed huge $V_{th}$ shift in the negative direction. $V_{th}$ shift decreases from 10 to -28.2V as Indium composition ratio is increased. Because the free electron density is increased according to variation of the Indium composition ratio.

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Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

  • Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.11-20
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    • 2008
  • The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

Effects of Vth adjustment ion implantation on Switching Characteristics of MCT(MOS Controlled Thyristor) (문턱전압 조절 이온주입에 따른 MCT (MOS Controlled Thyristor)의 스위칭 특성 연구)

  • Park, Kun-Sik;Cho, Doohyung;Won, Jong-Il;Kwak, Changsub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.69-76
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    • 2016
  • Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

Analog Performance Analysis of Self-cascode Structure with Native-Vth MOSFETs (Native-Vth MOSFET을 이용한 셀프-캐스코드 구조의 아날로그 성능 분석)

  • Lee, Dae-Hwan;Baek, Ki-Ju;Ha, Ji-Hoon;Na, Kee-Yeol;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.8
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    • pp.575-581
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    • 2013
  • The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

Computing-Inexpensive Matrix Model for Estimating the Threshold Voltage Variation by Workfunction Variation in High-κ/Metal-gate MOSFETs

  • Lee, Gyo Sub;Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.96-99
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    • 2014
  • In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

Tramadol as a Voltage-Gated Sodium Channel Blocker of Peripheral Sodium Channels Nav1.7 and Nav1.5

  • Chan-Su, Bok;Ryeong-Eun, Kim;Yong-Yeon, Cho;Jin-Sung, Choi
    • Biomolecules & Therapeutics
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    • v.31 no.2
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    • pp.168-175
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    • 2023
  • Tramadol is an opioid analog used to treat chronic and acute pain. Intradermal injections of tramadol at hundreds of millimoles have been shown to produce a local anesthetic effect. We used the whole-cell patch-clamp technique in this study to investigate whether tramadol blocks the sodium current in HEK293 cells, which stably express the pain threshold sodium channel Nav1.7 or the cardiac sodium channel Nav1.5. The half-maximal inhibitory concentration of tramadol was 0.73 mM for Nav1.7 and 0.43 mM for Nav1.5 at a holding potential of -100 mV. The blocking effects of tramadol were completely reversible. Tramadol shifted the steady-state inactivation curves of Nav1.7 and Nav1.5 toward hyperpolarization. Tramadol also slowed the recovery rate from the inactivation of Nav1.7 and Nav1.5 and induced stronger use-dependent inhibition. Because the mean plasma concentration of tramadol upon oral administration is lower than its mean blocking concentration of sodium channels in this study, it is unlikely that tramadol in plasma will have an analgesic effect by blocking Nav1.7 or show cardiotoxicity by blocking Nav1.5. However, tramadol could act as a local anesthetic when used at a concentration of several hundred millimoles by intradermal injection and as an antiarrhythmic when injected intravenously at a similar dose, as does lidocaine.

Analysis of Electrical Characteristics for Double Gate MOSFET (Double Gate MOSFET의 전기적 특성 분석)

  • 김근호;김재홍;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.261-263
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    • 2002
  • CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

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Study on the Reliability of an OLED Pixel Circuit Using Transient Simulation (과도상태 시뮬레이션을 사용한 OLED 픽셀 회로의 신뢰성 분석 방안 연구)

  • Jung, Taeho
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.4
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    • pp.141-145
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    • 2021
  • The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (Vth) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take Vth shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent Vth shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but Vth shifts from all TFTs in a pixel need to be considered to improve long-time reliability.