Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Analog Performance Analysis of Self-cascode Structure with Native-Vth MOSFETs

Native-Vth MOSFET을 이용한 셀프-캐스코드 구조의 아날로그 성능 분석

  • Lee, Dae-Hwan (Department of Semiconductor Engineering, Chungbuk National University) ;
  • Baek, Ki-Ju (Department of Semiconductor Engineering, Chungbuk National University) ;
  • Ha, Ji-Hoon (Department of Semiconductor Engineering, Chungbuk National University) ;
  • Na, Kee-Yeol (Department of Semiconductor Electronics, Chunbuk Provincial College) ;
  • Kim, Yeong-Seuk (Department of Semiconductor Engineering, Chungbuk National University)
  • 이대환 (충북대학교 반도체공학과) ;
  • 백기주 (충북대학교 반도체공학과) ;
  • 하지훈 (충북대학교 반도체공학과) ;
  • 나기열 (충북도립대학 반도체전자전공) ;
  • 김영석 (충북대학교 반도체공학과)
  • Received : 2013.07.02
  • Accepted : 2013.07.09
  • Published : 2013.08.01
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Abstract

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

Keywords

References

  1. S. S. Rajput and S. S. Jamuar, IEEE Circuits and Systems Mag., 2, 24 (2002).
  2. C. G-Montoro, M. C. Schneide, and I. J. B. Loss, J. of Solid State Circuits, 29, 1094 (1994). https://doi.org/10.1109/4.309905
  3. R. Castello, A. G. Grassi, and S. Donati, IEEE J. of Solid-State Circuits, 25, 669 (1990). https://doi.org/10.1109/4.102659
  4. I. Fujimori and T. sugimoto, IEEE J. of Solid-State Circuits, 33, 1863 (1998). https://doi.org/10.1109/4.735525
  5. M. T. Sanz, S. Celma, B. Calvo, and D. Flandre, IEE Proc.-Circuits Devices Syst., 153, 461 (2006). https://doi.org/10.1049/ip-cds:20060058
  6. K. J. Baek, J. M. Gim, H. S. Kim, K. Y. Na, N. S. Kim, and Y. S. Kim, Electron. Letts., 49, 591 (2013). https://doi.org/10.1049/el.2013.0554
  7. R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd ed. (John Wiley & Sons, New Jersey, 2010) p.287.
  8. J. M. Gim, D. H. Lee, K. J. Baek, K. Y. Na, and Y. S. Kim, J. KIEEME, 26, 278 (2013).
  9. K. J. Baek, J. K. Kim, Y. S. Kim, and K. Y. Na, Trans. Electr. Electron. Mater., 11, 1 (2010). https://doi.org/10.4313/TEEM.2010.11.1.001