• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.487-487
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• 2013

According to shrinkage of transistor, interface traps have been recognized as a major factor which limits the process development in manufacturing industry. The traps occur through spontaneous generation process, and spread into the forbidden band. There is a large change of current though a few traps are existed at the Si-SiO2 interface. Moreover, the increased temperature largely affects to the leakage current due to the interface trap. For this reason, we made an effort to find out the relationship between temperature and interface trap. The subthreshold swing (SS) was investigated to confirm the correlation. The simulated results show that the sphere of influence of trap is enlarged according to increase in temperature. To investigate the relationship between thermal energy and surface potential, we extracted the average surface potential and thermal energy (kT) according to the temperature. Despite an error rate of 6.5%, change rates of both thermal energy and average surface potential resemble each other in many ways. This allows that SS is affected by the trap within the range of the thermal energy from the surface energy.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• 한국진공학회지
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• 제11권4호
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• pp.230-234
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• 2002

고온 급속 열처리를 행한 $LiNbO_3Si$/(100) 구조를 가지고 여러 가지 전극을 사용하여 금속/강유전체/반도체 커패시터를 제작하였으며, 제작한 커패시터의 비휘발성 메모리 응용 가능성을 확인하였다. MFS 커패시터의 C-V 특성 곡선에서는 LiNbO$_3$박막의 강유전성으로 인한 히스테리시스 특성이 관측되었으며, 1 MHz C-V 특성 곡선의 축적 영역에서 산출한 비유전율은 약 25 이었다. Pt 전극을 사용하여 제작한 커패시터에서는 인가 전계 500 kV/cm 범위에서 $1\times10^{-8}$ A/cm 이하의 우수한 누설전류 특성이 나타났다. midgap 부근에서의 계면 준위 밀도는 약 $10^{11}\textrm{cm}^2$.eV 이었으며, 잔류분극 값은 약 1.2 $\muC/\textrm{cm}^2$ 였다. Pt 전극과 A1 전극 모두 500 kHz 주파수의 바이폴러 펄스를 인가하면서 측정한 피로 특성에서 $10^{10}$ cycle 까지 측정된 잔류 분극 값이 초기 값과 같았다.

• 한국결정학회:학술대회논문집
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• 한국결정학회 2007년도 추계학술연구발표회 및 정기총회
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• pp.42-42
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.266-272
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• 2009

In the present work three dimensional process and device simulations were employed to study the performance variations with RTA. It is observed that with the increase in RTA temperature, the arsenic dopants from the source /drain region diffuse laterally under the spacer region and simultaneously acceptors (Boron) are redistributed from the central axis region of the fin towards the Si/SiO2 interface. As a consequence both drive current and peak cut-off frequency of an n-FinFET are observed to improve with RTA temperatures. Volume inversion and hence the flow of carries through the central axis region of the fin due to reduced scattering was found behind the performance improvements with increasing RTA temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.48-51
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• 1995

We have developed the three dimensional mesh generator for three dimensional process simulation using the FEM(Finite Element Method). Tetrahedron element construct the presented three dimensional mesh, which is suitable for the simulation of three dimensional behavior of the LOCOS. The simulation of thermal oxidation is one of the problem in scale downed semiconductor processes. As three dimensional simulators use the huge size of the memory, we use the efficient method that generates the new nodes inside the growing oxide and removes the nodes nearby the SiO2/Si interface in silicon. The resented three dimensional mesh generator was designed to be used in various process simulations, for instance thermal oxidation, silicidation, nitridation, ion implantation, diffusion, and so on.

• 대한전자공학회논문지
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• 제25권7호
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.32-40
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• 2004

An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the $Si/SiO_2$ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.574-574
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• 2012

We report a simple way of fabricating high-quality carbon nanoscrolls (CNSs) by taking advantage of strain relief due to large difference in strain at the interface of graphene and underlying layer. This method allows strain-controlled self rolling-up of monolayer graphene during etching process at predefined positions on SiO2/Si substrates by photolithography. The size and the length of the CNSs can be easily controlled by adjusting the thickness of the underlying layer and by pre-patterning. Raman spectroscopy studies show that the CNSs is free of significant defects, and the electronic structure and phonon dispersion are slightly different from those of two-dimensional graphene. The preparation of high-quality CNSs may open up new opportunities for both fundamental and applied research of CNSs.

• Transactions on Electrical and Electronic Materials
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• 제5권6호
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• pp.211-214
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• 2004

We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidationenhanced diffusion in silicon and has segregation coefficients at the $Si/SiO_2$ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data and $0.13 {\mu}m$ device characteristics such as $V_{th}$ and $Id_{sat}$ with errors less than $5 \%$ between simulation and experiment.