It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

본 논문에서는 클록의 duty ratio가 변하였을 때, 그 클록의 duty ratio를 $50\%$의 duty ratio로 만들어 주는 Pulse Width Control Loop Circuit을 설계하였다. 기존의 논문에서는 duty ratio를 변화시키기 위해 각 duty ratio 마다 알맞은 제어 전압을 공급해하는 문제점이 있었다. 본 논문은 제어 전압이 변하지 않고 일정한 전압으로도 duty ratio를 변화시킬 수 있게 하여, 제어 전압 변화에 대한 문제점을 해결하였다. 설계, 시뮬레이션 결과 기존의 논문보다 간단해진 회로 구성으로 더욱 높은 주파수에서 동작하였다. 그리고 settling 시간도 기존의 논문의 l00ns 이상에서 5ns로 줄어듦을 확인할 수 있었다. 본 논문은 3.3V의 공급 전압에서 $0.35{\mu}m$ CMOS공정을 이용하여 설계하였고 동작 주파수는 500MHz-2GHz였고, settling 시간은 10n이하였다.

We suggest Q-band MEMS MIMIC (Millimeter wave Monolithic Integrated Circuit) HEMT Oscillator using DAML (Dielectric-supported Airgapped Mcrostrip Line) structure. We elevated the signal lines from the substrate using dielectric post, in order to reduce the substrate dielectric loss and obtain low losses at millimeter-wave frequency. These DAML are composed with heist of $10\;{\mu}m$ and post size with $20\;{\mu}m\;{\times}\;20\;{\mu}m$. The MEMS oscillator was successfully integrated by the process of $0.1\;{\mu}m$ GaAs PHEMTs, CPW transmission line and DAML. The phase noise characteristic of the MEMS oscillator was improved more than 7.5 dBc/Hz at a 1 MHz offset frequency than that of the CPW oscillator And the high output power of 7.5 dBm was measured at 34.4 GHz.

본 논문은 밀리미터파 대역 무선통신 시스템 송신부의 응용을 위해 CPW 구조를 이용하여 V-band용 상향 주파수 혼합기와 2단 구동증폭기를 설계$\cdot$제작하였다. 능동소자는 본 연구실에서 제작한 $0.1{\mu}m$ 게이트 GaAs Pseudomorphic HEMTs(PHEMTs)를 사용하였으며 입$\cdot$출력단은 CPW를 사용해 정합 회로를 설계하였다. 제작된 상향 주파수 혼합기는 LO power 5.4 dBm, 2.4 GHz IF 신호를 -10.25 dBm으로 입력하였을 때 Conversion Loss 1.25 dB, LO-to-RF Isolation은 58 GHz에서 13.2 dB의 특성을 나타내었다 2단 구동 증폭기는 측정결과 60 GHz에서 S21 이득 13 dB, $58\;GHz\;\~\;64\;GHz$ 대역에서 S21 이득 12 dB 이상을 유지하는 광대역 특성을 얻었고 증폭기의 Pl dB는 3.8 dBm, 최대 출력전력은 6.5 dBm의 특성을 얻었다.

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

The substrate parameters of Si MOSFET equivalent circuit model were directly extracted from measured S-Parameters in the GHz region by using simple 2-port parameter equations. Using the above extract ion method, bias and gate length dependent curves of substrate parameters in the RF region are obtained by varying drain voltage at several short channel devices with various gate lengths. These extract ion data will greatly contribute to scalable RF nonlinear substrate modeling.

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

Electron beam on high energy acceleration, which travels deeply and sharply through photoresist, became to be used in e-beam lithography apparatus for nano-patterning in due to its high resolution. An advanced electron beam lithography simulation tool is currently undergoing development for nano-patterning. This paper will demonstrate such simulation efforts with experiments at 200 keV e-beam lithography processes on PMMA, ZEP520 of which photoresist parameters and characteristics will be explained with simulation results. Neureuther parameters was extracted from the contrast curve of the resist

PZT thin films were formed by rf-magnetron sputtering on $Pt/Ti/SiO_2/Si$ substrate. Bulk PZT target containing $5\%$ excess PbO was used. They were formed with in-situ process at $650^{\circ}C$ as total thickness of 175 and 250 nm after the depositing of thin PZT films at room temperature, i. e. 2-step Sputtering. It was found that the ferroelectric perovskite phase is formed at $650^{\circ}C$ by XRD and the interface between room temp.-layer and $650^{\circ}C$ -layer is not existent. In the samples undergoing 2-step sputtering the dielectric constant was 600 or more and the leakage current density was $2{\times}10^{-7}A/cm^2$. So, we found that the room temp.-layer on the bottom electrode stabilize the underlaid layers.

We fabricated PLT(5) thin film on $Pt/TiO_x/SiO_2/Si$ substrate by using sol-gel method and investigated leakage current, switching and retention properties. The leakage current density of PLT(5) thin film was $3.56{\times}10^{-7}A/cm^2$ at 4V. In the examination of switching properties, pulse voltage and load resistance were $2V{\~}5V$ and $50{\Omega}{\~}3.3k{\Omega}$, respectively. Switching time had a tendency to decrease from 520ns to 140ns with the increase of pulse voltage, and also the time was increased from 140ns to $13.7{\mu}s$ with the increase of load resistance. The activation energy obtained from the relation of applied pulse voltage and switching time was about 143kV/cm. The error of switched charge density between hysteresis loop and experiment of polarization switching was about $10\%$. Also, polarization in retention was decreased as much as about $8\%$ after $10^5$s.

In this paper, Ni Germane-silicide formed on undoped $Si_{0.8}Ge_{0.2}$ as well as source/drain dopants doped $Si_{0.8}Ge_{0.2}$ was characterized by the four-point probe for sheet resistance. x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and field emission scanning electron microscope (FESEM). Low resistive NiSiGe is formed by one step RTP (Rapid thermal processing) with temperature range at $500{\~}700^{\circ}C$. To enhance the thermal stability of Ni Germane-silicide, Ni/Co/TiN structure with different Co concentration were studied in this work. Low sheet resistance was obtained by Ni/Co/TiN structure with high Co concentration using 2-step RTP and it almost keeps the same low sheet resistance even after furnace annealing at $650^{\circ}C$ for 30 min.

In this paper, we fabricated pantacene TFTs using PVP copolymer and cross-linked PVP as gate insulator on glass and plastic (PET) substrate. Depending on the density of PVP and poly (melamine-co-formaldehyde) the performance has been changed. We obtained the best performance with the mobility of 0.12cm2/V sec and the on/off current ratio of $1.19{\times}10^6$ for the case of $10wt\%$ PVP copolymer mixed with $5wt\%$ poly(melamine-co-formaldehyde). Additionally using OTFTs with the above PVP gate insulator, we fabricated the integrated circuit including inverter which produced the gain of 5.56 on the glass substrate and gain of 9.7 on the plastic (PET) substrate. And the threshold voltage was respectively +8V and +14v$ldots$

In this paper we fabricated a test panel for AMOLED on glass and PET substrate. The test panel consisted of the various size of OTFTs and OLEDs and the current driving capability of OTFTs for OLEDs has been investigated. OTFTs were made of the inverted staggered structure and employed polyvinylphenol (PVP) as the gate insulator and pentacene thin film as the active layer. The OTFTs produced the filed effect mobility of $0.3 cm^2/V.sec$ and on/off current ratio of $10^5$. OLEDs consisted of TPD for HTL and Alq3 for EML with 35nm thick, generating green monochrome light. We found that OTFT with channel length of 70${\mu}m$ and channel width of over 3.5mm provided the sufficient current to OLED to generate the luminescence of $0.3Cd/m^2$.

The one of important requisites for fabricating molecular electronic device is the single crystal direction of bottom substrate nowadays. [1,2]. We obtain the optimum SAM result when the Au crystal is <111> structure for Self-Assembled molecular. To get the <111> crystal Au, we generally repeat heating and cooling course after evaporating Au [3]. However, we can fabricate <111> crystal Av thin film except post treatment because we simultaneously evaporate and anneal using Effusion Cell. In this paper, we study on thin film growth of <111> crystal Au as bottom electrode which is essential for Self-Assembled molecular by Effusion Cell and analyze crystal structure, thickness, surface conductivity and so on as each process condition.

Thick film alcohol gas sensors were fabricated. Their electrical properties and gas sensing characteristics were investigated. The sensitivity of $1wt.\%$ Pd-doped ${\gamma}-Fe_2O_3$ thick film heat treated at $400^{\circ}C$, 2hrs was $74\%$ to 500ppm alcohol gas at the operating temperature of $250^{\circ}C$. The selectivity of the film to alcohol was good. It showed fast response time to low concentrations of alcohol in air, hence this sensor can be used as a breath sensor.

In this study, highly thermal stable Ni Germanosilicide has been utilized using NiPt alloy and novel NiPt/Co/TiN tri-layer. And, the Ni Germanosilicide Properties were characterized according to different Ge ratio (x) in $Si_{l-x}Ge_x$ for the next generation CMOS application. The sheet resistance of Ni Germanosilicide utilizing pure-Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30 min. Moreover, more degradation was found as the Ge fraction increases. However, using the proposed NiPt/Co/TiN tri-layer, low temperature silicidation and wide range of RTP process window were achieved as well as the improvement of the thermal stability according to different Ge fractions by the subsequent Co and TiN capping layer above NiPt on the $Si_{l-x}Ge_x$. Therefore, highly thermal immune Ni Germanosilicide up to $600^{\circ}C$ for 30 min is utilized using the NiPt/Co/TiN tri-layer promising for future SiGe based ULSI technology.

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gun control were proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0mA to 300mA over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than $1.4\%$ over the current range from 0A to 300mA.

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

This paper describes an IP design and implementation of a complicated hardware to System on a Chip(SoC) to simplify the complicated system. As using SoC, hardware and software can be designed and verified both. This paper describes an image capturing IP and a perpendcular coordinate robot IP that can move on x, y coordinates. 240$\ast$320 TFT-LCD is used to display images.

This paper describes an embedded system to put a SoC actuator IP in motion and linux drivers. The If that a embedded linux among embedded OS is ported is implemented as linux driver. The actuator IP is controlled by application programming. To make users use this easily, a QT is ported on the system. Application program can operate the actuator IP device driver on TFT LCD.

This paper introduces a modulation method for digital wireless communication based on general DS-QPSK. The design and fabrication is for home networking application to a typical RF transmitter with DS-QPSK modulator. This modulator implemented using VHDL hardware programming language, the fabrication of IC chip $5{\times}5 mm^2$ was carried by 27th IDEC MPW(Multi Project Wafer) process in 0.35${\mu}m$ rule at Samsung Inc. This paper presented the important of this technology for the future application in wireless sensor. This module can be efficient usage for home network to transmit the RF wireless sensor system.

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

본 논문에서는 저 전력 마이크로프로세서를 개발하기 위해 ARM7 마이크로프로세서와 명령어 호환을 갖는 32비트 RISC 구조의 마이크로프로세서를 설계하였다. 저 전력 ARM7 마이크로프로세서 IP 구현을 위하여 새로운 정수 나눗셈 명령어를 정의하고 이를 적용하는 회로를 설계하여 제수가 피제수보다 큰 경우 6.4nW, 그 이외의 경우에는 76.5 nW를 소모하여 기존의 방법보다 $140{\~}860\%$ 까지 개선되었음을 측정하였다. 또한 Multi-cycle 명령어 발생시 Prefetch에 의한 전력 소모를 줄이기 위하여 명령어의 condition code를 미리 결정함으로써 $50\%$의 prefetch 동작 횟수를 줄였다. 그 결과 저 전력 파이프라인의 경우에는 1.943mW/1MHz의 소비 전력이 측정되었다.

본 논문에서는 로드 명령어 처리와 곱셈기의 구조를 개선한 ARM9 호환 마이크로프로세서를 설계하였으며, ARM9 마이크로프로세서와 비교하여 특정한 로드 명령어 수행 시 1 클록 사이클을 단축하였고, 곱셈명령어 수행 시 2 클록 사이클 단축하였다. 설계된 ARM9 프로세서는 VHDL로 기술하였으며, 명령어 시뮬레이션 결과 ARM9 마이크로프로세서 시뮬레이터와 실행 결과 값이 동일함을 확인하여 명령어 호환 검증을 하였으며, Xilinx FPGA를 이용하여 66MHz 동작환경에서 실시간 영상 처리 수행을 검증하였다.

In this paper we present about implementation of channel coder and Viterbi decoder for Mobile communication & IEEE 802.11a Wireless LAN. In the IEEE 802.11a Wireless LAN decoding provided that Viterbi algorithm and convolutional encoder by constraint k=7, ($133_8,\;171_8$) for channel error correction. This Paper presents a novel survivor memory management and decoding techniques with sequential backward state transition control in the trace-back Viterbi decoder, In order to verification we provide to the examples of circuit design and decoding results.

This paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance. decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor sire is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using $0.18 {\mu}m$ process-based-HSPICE simulation.

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

Short channel IC circuits become increasingly important in modern high performance electronic systems. In this paper, parts of an analog hearing aid, an amplifier and a regulator, which are implemented with short channel CMOS devices, are designed and optimized in its performance.

The modeling circuit becomes more important in developing various magnetic devices regarding the fact that the competitive architecture and circuitry should be developed simultaneously. In this paper, we introduce a modeling circuit for hysteresis characteristic of a magnetic device, which is a major characteristic in the spin dependent magnetic material. This transistor-level model is conspicuous in that it can be usefully embodied in real circuits rather than conventional SPICE models are only for simulations.

The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.

We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of $67.8\%$ glitch reduction and $32.0\%$ power reduction by simultaneous gate freezing, gate sizing, and buffer insertion.

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

AS supply voltage of DRAM is scaled down, voltage circuit that is stable from external noise is more important. $V_{PP}$ voltage is very important, it is biased to gate of memory cell transistor and possible to read and write without voltage down. It has both high pump gain and high power efficiency therefore charge pump circuit is proposed. The circuit is simulated by 0.18${\mu}m$ memory process and 1.2V supply voltage. Compare to CCTS, it is improved 0.43V of pump gain, $3.06\%$ of power efficiency at 6 stage.

We studied the characteristics of impedance and electromechanical coupling coefficient in ZnO and AIN thin films by using resonance frequency spectrum method. The response peak of impedance decreased with the decrease of thickness of piezoelectrics, the number of mode of response peak increased with the increase of substrate thickness. An error of $k_{t}^{2}$ estimated from input $k_{t}^{2}$ increased as the thickness of piezoelectrics decreased and the thickness of substrate increased. Also, the error was increased in case of a large acoustic impedance of substrate. It was found that the composite resonator operating in optimized condition could be designed through the resonance frequency spectrum analysis of composited resonator consisted of piezoelectric thin film and substrate.

To make production and equipment investment plans in semiconductor Line, implementation of many variables is needed. But these factors could bring many changes and the result is hard to predict. Because prediction is hard, it is hard to make a standard. So this project established Semiconductor production plans using LP Algorithm to satisfy all the conditions from the factors and came up with thesis on reasonable and standardized process.

As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

In this paper, we demonstrate polymer thin-film transistors (TFTs) on a paper-based flexible substrate. As a substrate, commercially available photo-paper is used with Parylene coating. The parylene layer enables conventionally used wet chemical process and vacuum deposition processes for electrodes and gate insulator. As an active channel layer, we used poly-3-hexylthiophene (P3HT) which is solution process. Field effect mobility up to $(0.06 {\pm} 0.02) cm^2/Vs$ and on/off ratio of $10^3 {\~}10^4$ are achieved on a photo-paper.

Recently, organic thin films are widely used to the application of organic optoelectronic devices such as OLED, OTFT, organic solar cell, and organic laser, etc. The electrical transport of organic thin film is very important to determine the performance and thus should be analyzed for analysis of operation and design of devices. However, there have been rarely known about the electrical transport of organic thin films. As an example pentacene is known to be a good organic semiconductor to produce the best performance in OTFT at the present. But the performance is varied depending on the position of source/drain contacts and gate surface states and the thickness of thin film. Therefore, it is necessary to investigate the effects of the above-mentioned factors on the electrical properties of pentacene thin film.

In this paper, we developed a new photolithography process which used a water-soluble photoresist instead of organic solvent soluble photoresist, defined pentacene thin film. And pentacene OTFTs were fabricated with the water- soluble photolithography process.

High quality GaN layer was obtained on 0001 sapphire substrate using ammonia($NH_3$) as a nitrogen source by gas source molecular beam epitaxy. As a result, RHEED is used to investigate the relaxation processes which take place during the growth of GaN. In-situ RHEED(reflection high electron energy diffraction) appeared streaky-like pattern. The full Width at half maximum of the x-ray diffraction(FWHM) rocking curve measured from plane of GaN has exhibited as narrow as 8arcmin and surface roughness was 7.83nm. Photoluminescence measurement of GaN was investigated at room temperature, where the intensity of the band edge emission is much stronger than that of deep level emission. The GaN epitaxy layer according to various growth condition was investigated.

Gate length dependent data of intrinsic MOSFET equivalent circuit parameters are extracted using a direct extraction technique based on simple 2-port parameter equations. The relatively scalable data with respect to gate length are obtained. These data are verified to be acrurate by observing good correspondence between modeled and measured S-parameters up to 30GHz. These data will be helpful to construct RF scalable MOSFET model.

This paper proposed a new solid State Relay(SSR) structure that can replace the conventional SSR as a power IC. The photodiode arrays, the main part of this structure, were designed and integrated in the same power It chip with the output parts, LDMOSFET and BJT, on a SOI substrate. The fabrication of this input part shared the same output LDMOSFET fabrication processs, except the additional deposition of Silicon nitride($Si_3N_4$) for the photo-detection part. According to LED illumination intensites and photo detecting areas, we could obtain voltage of 0.49V ${\~}$0.52V and current of 5.5uA ${\~}$ 108uA respectively from the fabricated unit photodiode. The maximum value of the voltage and the current we could obtain from the photodiode array were 3.58V and 24.4uA respectively, and the voltage was enough to operate the output LDMOSFET

본 논문에서는 $20\%$ Ge 조성 비율을 갖는 SiGe 200nm 에 $1\%$-Nitrogen doping 된 Nickel 을 이용하여 새로운 Nickel Germanosilicide 방법을 제안하여 Ni-Germanosilicide 의 단점인 열 안정성 개선에 대해 연구하였다. Nitrogen atom 이 grain boundary 에 존재하여 Nickel의 diffusion을 억제시키는 역할을 하여 shallow한 실리사이드와 uniform 한 실리사이드 계면 특성을 얻게 되었다. 그리고 실리사이드 형성 후, 고온로 열처리 $600^{\circ}C$, 30min 후에도 낮고 안정한 면 저항 특성으로 열안정성 개선 할 수 있다.

Organosilicate films are promising porous low-dielectric materials, which can replace the silicon dioxide films. It was researched that organosilicate films have two different chemical shifts according to the increase of the flow rate ratio. There are the red shift due to the electron deficient substitution group, and the blue shift of the electron rich substitution group. Among these chemical shifts, the blue shift from $1000 cm^{-1}$ to $1250 cm^{-1}$ was related with the formation of pores. The methyl radicals of the electron-rich substitution group terminate easily the Si-O-Si cross-link, and the Si-O-C cage-link near $1057 cm^{-1}$ is originated from the cross-link breakdown due to much methyl radicals.

For implementation of Cryptographic algorithms, security against implementation attacks such as side-channel attacks as well as the speed and the size of the circuit is important. Power Analysis attacks are powerful techniques of side-channel attacks to exploit secret information of crypto-processors. In this thesis the FPGA implementation of versatile elliptic crypto-processor is described. Explain the analysis of power consumption of ALTERA FPGA(FLEX10KE) that is used in our hand made board. Conclusively this thesis presents clear proof that implementations of Elliptic Curve Crypto-systems are vulnerable to Differential Power Analysis attacks as well as Simple Power Analysis attacks.

Manchester encoder of FSM method is a suitable signal coding for an RFID system. However, Manchester encoder of FSM method has usually more gate count and lower maximum frequency than encoder of exclusive-OR gate method. In this paper. it is proposed encoder of FSM method to improve gate count and maximum frequency.

The ECC(Elliptic Curve Cryptogrphics), one of the representative Public Key encryption algorithms, is used in Digital Signature, Encryption, Decryption and Key exchange etc. The key operation of an Elliptic curve cryptosystem is a scalar multiplication, hence the design of a scalar multiplier is the core of this paper. Although an Integer operation is computed in infinite field, the scalar multiplication is computed in finite field through adding points on Elliptic curve. In this paper, we implemented scalar multiplier in Elliptic curve based on the finite field GF($2^{163}$). And we verified it on the Embedded digital system using Xilinx FPGA connected to an EISC MCU. If my design is made as a chip, the performance of scalar multiplier applied to Samsung $0.35 {\mu}m$ Phantom Cell Library is expected to process at the rate of 8kbps and satisfy to make up an encryption processor for the Embedded digital doorphone.

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation. we present an Interpolation type architecture. In order to overcome the problems of high speed operation further a novel encoder, a circuit for the Reference Fluctuation, an Averaging Resistor and a Track & Hold for the improved SNR are proposed. The proposed Interpolation ADC consists of Track & Holt four resistive ladders with 64 taps, 32 comparators and digital blocks. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply.

This paper presents a new circuit panitioning algorithm using wire redundancy removal. This algorithm consist of the two steps. In the first step. We propose a new IIP(Iterative Improvement Partitioning) technique that selects the method to choice cells according to improvement status using two kinds of bucket structures, the one kept by total gain, and the other by updated gain. In the second step, we select the target wire in the cut-set. We add a alternative wire in the circuit to remove the target wire. For this we use wire redundancy removal and addition method The experimental results on MCNC benchmark circuits show improvement up to $41-50\%$ in cut-size over previous algorithms

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

The thesis describes the design of 12bit digital-to-analog converter (DAC) which shows the conversion rate of 500MHz and the power supply of 3.3V with 0.35${\mu}m$ CMOS 1-poly 4-metal process for advanced wireless transceiver of high speed and high resolution. The proposed DAC employes segmented structure which consists of 6bit MSB, 3bit mSB, 3bit LSB for area efficiency Also, using a optimized aspect ratio of process and new triple diagonal symmetric centroid sequence for high yield and high linearity. The proposed 12bit current mode DAC was employs new deglitch circuit for the decrement of the glitch energy. Simulation results show the conversion rate of 500MHz, and the power dissipation of 85mW at single 3.3V supply voltage. Both DNL and INL are found to be smaller than ${\pm}0.65LSB/{\pm}0.8LSB$.

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

In this study, we design the one-chip PWM IC for SMPS (Switching Mode Power Supply) application. We determine the IC spec. and simulated each block of PWM IC (Reference, Error amp., Comparator, Oscillator) with Smart Spice (SILVACO Circuit Simulation Tool). Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain (${\simeq}65dB$), unity frequency (${\simeq}190kHz$) and large PM($75^{\circ}$).Saw tooth generators operate with 20K oscillation frequency (external resistor, capacitor).

The motion estimation which requires huge computation consumes large power in a video encoder. Although a number of fast-search algorithms are proposed to reduce the power consumption, the smaller the computation, the worse the performance they have. In this paper, we propose an architecture that a low energy management scheme can be applied with several fast-search algorithm. In addition. we show that ECVH, a software scheduling scheme which dynamically changes the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget, can be applied to the architecture, and show that the power consumption can be reduced.

This paper proposes effective method for delay estimation in RLC interconnects. This method is simple, but precise. The results using the proposed method for RLC circuits show that absolute average relative error is within $7\%$ with the exception of first node in comparison with HSPICE results.

This paper presents a 12-Bit 250MHz CMOS current-mode Digital to Analog Converter(DAC) with current scalers and dividers. It consist of 4 MSB current scaler, 4 MLSB current divider, and 4 LSB current divider. The simulation results show a conversion rate of 250MHz, DNL/INL of ${\pm}5LSB/{\pm}7LSB$, die area of $0.55mm^2$ and Power dissipation of 27mW at 3.3V

This paper proposes an analytic method that can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

Our paper focus on crosstalk noise problem, especially crosstalk glitch that occurs when victim is stable state and aggressor is transitive state. This generated glitch weigh with the functional reliability if the glitch is considerable. In this paper, we use buffer insertion, down sizing, buffer insertion with up-sizing methods concurrently. These methodologies use filtering effects which gates that have bigger noise margin than glitch width eliminates glitch. In addition, we do limited optimization in boundary of node's slack. Therefore, the operated node's changes are for nothing in other node's slack.

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average $8.64\%$ Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

The CORDIC algorithm can be implemented very simple H/W, but needs a lot of latency to compute trigonometric function. The RA(Redundant Arithmetic) resolves this problem, but also has difficulty to determine the directions of micro-rotations. The pre-computed direction of micro-rotation algorithm relieves the RA of this matter. In this paper, we proposed the modified the pre-computed algorithm adopted with a table-lookup. Instead of reducing H/W complexity, its performance and calculation errors are improved.

This paper presents a low power design of the embedded 3D graphics rendering processor with the double span processing stage. The increase of hardware complexity by using the double span processing stage is ignorable. And the performance is equal to the rendering processor with the single span processing stage. It reduces the power consumption by using different clock frequencies.

In this paper. the soft IP (Intellectual Property) of pipeline of 32-bit microcontroller for embedded and portable application is presented. This IP supports variable pipeline stage according to the performance that user wants. In this architecture, three pipeline stages are basically employed and extended to the five pipeline stages. To this purpose, control logic has been partitioned to reflect each pipeline stage. FPGA platform is used for rapidly prototyping the IP. This is designed using Verilog HDL

In this paper, we propose a driving circuit that can be operated with a lower voltage than that of the conventional circuit without reducing the discharge voltage. the circuit proposed in this paper has a merit to improve the electrical characteristics because it can be composed of switching devices with low voltage. The operation and efficiency using real devices. The features of the circuit proposed in this paper are as follows; the power loss can be decreased by the use of low voltage, the cost if the driving circuit for PDP can be reduced by the use of switching devices operated with low voltage.

A $Pt/Al_xGa_{l-x}N$ Schottky type Ultra-violet photodetector was modeled and simulated using the commercial SILVACO software program. In the carrier transport, we applied field model and other analytic model to determine the electron saturation velocity and low field mobility for GaN and $Al_xGa_{l-x}N$. A C-Interpreter function was defined to described the mole-fraction for the ternary compound semiconductor such as $Al_xGa_{l-x}N$. As comparing the simulated and experimental results, we found that the simulated result for type-1 has $15.9 nA/cm^2$ of leakage current at 5V. We confirmed a good agreement of photo-current in the UV Photo-detector, while applying the absorption coefficient and reflective index of active $Al_xGa_{l-x}N$ and other layers. There had been an intensive search for the proper refractive indices of the layers.