Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Verification of the Motion Estimation and Compensation Unit Using Full Search Algorithm

전역탐색 알고리즘을 이용한 움직임 추정 보상부 설계 및 검증

  • Jin Goon-Seon (Dept, of Telecommunication engineering Cheju National University) ;
  • Kang Jin-Ah (Dept, of Telecommunication engineering Cheju National University) ;
  • Lim Jae-Yoon (Dept, of Telecommunication engineering Cheju National University)
  • 진군선 (제주대학교 통신공학과) ;
  • 강진아 (제주대학교 통신공학과) ;
  • 임재윤 (제주대학교 통신컴퓨터 공학부)
  • Published : 2004.06.01
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Abstract

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

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